/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_DDR_REGISTERS_H__
#define __HW_DDR_REGISTERS_H__

#include "regs.h"

/*
 * MK70F12 DDR
 *
 * DRAM Controller
 *
 * Registers defined in this header file:
 * - HW_DDR_CR00 - DDR Control Register 0
 * - HW_DDR_CR01 - DDR Control Register 1
 * - HW_DDR_CR02 - DDR Control Register 2
 * - HW_DDR_CR03 - DDR Control Register 3
 * - HW_DDR_CR04 - DDR Control Register 4
 * - HW_DDR_CR05 - DDR Control Register 5
 * - HW_DDR_CR06 - DDR Control Register 6
 * - HW_DDR_CR07 - DDR Control Register 7
 * - HW_DDR_CR08 - DDR Control Register 8
 * - HW_DDR_CR09 - DDR Control Register 9
 * - HW_DDR_CR10 - DDR Control Register 10
 * - HW_DDR_CR11 - DDR Control Register 11
 * - HW_DDR_CR12 - DDR Control Register 12
 * - HW_DDR_CR13 - DDR Control Register 13
 * - HW_DDR_CR14 - DDR Control Register 14
 * - HW_DDR_CR15 - DDR Control Register 15
 * - HW_DDR_CR16 - DDR Control Register 16
 * - HW_DDR_CR17 - DDR Control Register 17
 * - HW_DDR_CR18 - DDR Control Register 18
 * - HW_DDR_CR19 - DDR Control Register 19
 * - HW_DDR_CR20 - DDR Control Register 20
 * - HW_DDR_CR21 - DDR Control Register 21
 * - HW_DDR_CR22 - DDR Control Register 22
 * - HW_DDR_CR23 - DDR Control Register 23
 * - HW_DDR_CR24 - DDR Control Register 24
 * - HW_DDR_CR25 - DDR Control Register 25
 * - HW_DDR_CR26 - DDR Control Register 26
 * - HW_DDR_CR27 - DDR Control Register 27
 * - HW_DDR_CR28 - DDR Control Register 28
 * - HW_DDR_CR29 - DDR Control Register 29
 * - HW_DDR_CR30 - DDR Control Register 30
 * - HW_DDR_CR31 - DDR Control Register 31
 * - HW_DDR_CR32 - DDR Control Register 32
 * - HW_DDR_CR33 - DDR Control Register 33
 * - HW_DDR_CR34 - DDR Control Register 34
 * - HW_DDR_CR35 - DDR Control Register 35
 * - HW_DDR_CR36 - DDR Control Register 36
 * - HW_DDR_CR37 - DDR Control Register 37
 * - HW_DDR_CR38 - DDR Control Register 38
 * - HW_DDR_CR39 - DDR Control Register 39
 * - HW_DDR_CR40 - DDR Control Register 40
 * - HW_DDR_CR41 - DDR Control Register 41
 * - HW_DDR_CR42 - DDR Control Register 42
 * - HW_DDR_CR43 - DDR Control Register 43
 * - HW_DDR_CR44 - DDR Control Register 44
 * - HW_DDR_CR45 - DDR Control Register 45
 * - HW_DDR_CR46 - DDR Control Register 46
 * - HW_DDR_CR47 - DDR Control Register 47
 * - HW_DDR_CR48 - DDR Control Register 48
 * - HW_DDR_CR49 - DDR Control Register 49
 * - HW_DDR_CR50 - DDR Control Register 50
 * - HW_DDR_CR51 - DDR Control Register 51
 * - HW_DDR_CR52 - DDR Control Register 52
 * - HW_DDR_CR53 - DDR Control Register 53
 * - HW_DDR_CR54 - DDR Control Register 54
 * - HW_DDR_CR55 - DDR Control Register 55
 * - HW_DDR_CR56 - DDR Control Register 56
 * - HW_DDR_CR57 - DDR Control Register 57
 * - HW_DDR_CR58 - DDR Control Register 58
 * - HW_DDR_CR59 - DDR Control Register 59
 * - HW_DDR_CR60 - DDR Control Register 60
 * - HW_DDR_CR61 - DDR Control Register 61
 * - HW_DDR_CR62 - DDR Control Register 62
 * - HW_DDR_CR63 - DDR Control Register 63
 * - HW_DDR_RCR - RCR Control Register
 * - HW_DDR_PAD_CTRL - I/O Pad Control Register
 *
 * - hw_ddr_t - Struct containing all module registers.
 */

//! @name Module base addresses
//@{
#ifndef REGS_DDR_BASE
#define HW_DDR_INSTANCE_COUNT (1U) //!< Number of instances of the DDR module.
#define REGS_DDR_BASE (0x400AE000U) //!< Base address for DDR.
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR00 - DDR Control Register 0
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR00 - DDR Control Register 0 (RW)
 *
 * Reset value: 0x20400000U
 */
typedef union _hw_ddr_cr00
{
    uint32_t U;
    struct _hw_ddr_cr00_bitfields
    {
        uint32_t START : 1;            //!< [0] Start
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t DDRCLS : 4;           //!< [11:8] DRAM Class
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t VERSION : 16;         //!< [31:16] Version
    } B;
} hw_ddr_cr00_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR00 register
 */
//@{
#define HW_DDR_CR00_ADDR         (REGS_DDR_BASE + 0x0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR00              (*(__IO hw_ddr_cr00_t *) HW_DDR_CR00_ADDR)
#define HW_DDR_CR00_RD()         (HW_DDR_CR00.U)
#define HW_DDR_CR00_WR(v)        (HW_DDR_CR00.U = (v))
#define HW_DDR_CR00_SET(v)       (HW_DDR_CR00_WR(HW_DDR_CR00_RD() |  (v)))
#define HW_DDR_CR00_CLR(v)       (HW_DDR_CR00_WR(HW_DDR_CR00_RD() & ~(v)))
#define HW_DDR_CR00_TOG(v)       (HW_DDR_CR00_WR(HW_DDR_CR00_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR00 bitfields
 */

/*!
 * @name Register DDR_CR00, field START[0] (RW)
 *
 * Initiates CMD processing in the memory controller.
 */
//@{
#define BP_DDR_CR00_START    (0U)          //!< Bit position for DDR_CR00_START.
#define BM_DDR_CR00_START    (0x00000001U) //!< Bit mask for DDR_CR00_START.
#define BS_DDR_CR00_START    (1U)          //!< Bit field size in bits for DDR_CR00_START.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR00_START field.
#define BR_DDR_CR00_START    (BITBAND_ACCESS32(HW_DDR_CR00_ADDR, BP_DDR_CR00_START))
#endif

//! @brief Format value for bitfield DDR_CR00_START.
#define BF_DDR_CR00_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR00_START), uint32_t) & BM_DDR_CR00_START)

#ifndef __LANGUAGE_ASM__
//! @brief Set the START field to a new value.
#define BW_DDR_CR00_START(v) (BITBAND_ACCESS32(HW_DDR_CR00_ADDR, BP_DDR_CR00_START) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR00, field DDRCLS[11:8] (RW)
 *
 * Defines the mode of operation of the memory controller.
 *
 * Values:
 * - 0000 - DDR
 * - 0001 - LPDDR
 * - 0010 - Reserved
 * - 0011 - Reserved
 * - 0100 - DDR2
 * - 0101 - Reserved
 * - 0110 - Reserved
 * - 1111 - Reserved
 */
//@{
#define BP_DDR_CR00_DDRCLS   (8U)          //!< Bit position for DDR_CR00_DDRCLS.
#define BM_DDR_CR00_DDRCLS   (0x00000F00U) //!< Bit mask for DDR_CR00_DDRCLS.
#define BS_DDR_CR00_DDRCLS   (4U)          //!< Bit field size in bits for DDR_CR00_DDRCLS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR00_DDRCLS field.
#define BR_DDR_CR00_DDRCLS   (HW_DDR_CR00.B.DDRCLS)
#endif

//! @brief Format value for bitfield DDR_CR00_DDRCLS.
#define BF_DDR_CR00_DDRCLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR00_DDRCLS), uint32_t) & BM_DDR_CR00_DDRCLS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DDRCLS field to a new value.
#define BW_DDR_CR00_DDRCLS(v) (HW_DDR_CR00_WR((HW_DDR_CR00_RD() & ~BM_DDR_CR00_DDRCLS) | BF_DDR_CR00_DDRCLS(v)))
#endif
//@}

/*!
 * @name Register DDR_CR00, field VERSION[31:16] (RO)
 *
 * Shows the version number of the memory controller. Reads as 0x2040.
 */
//@{
#define BP_DDR_CR00_VERSION  (16U)         //!< Bit position for DDR_CR00_VERSION.
#define BM_DDR_CR00_VERSION  (0xFFFF0000U) //!< Bit mask for DDR_CR00_VERSION.
#define BS_DDR_CR00_VERSION  (16U)         //!< Bit field size in bits for DDR_CR00_VERSION.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR00_VERSION field.
#define BR_DDR_CR00_VERSION  (HW_DDR_CR00.B.VERSION)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR01 - DDR Control Register 1
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR01 - DDR Control Register 1 (RO)
 *
 * Reset value: 0x00020B10U
 */
typedef union _hw_ddr_cr01
{
    uint32_t U;
    struct _hw_ddr_cr01_bitfields
    {
        uint32_t MAXROW : 5;           //!< [4:0] Maxmum Row
        uint32_t RESERVED0 : 3;        //!< [7:5] Reserved
        uint32_t MAXCOL : 4;           //!< [11:8] Maximum Column
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t CSMAX : 2;            //!< [17:16] Chip Select Maximum
        uint32_t RESERVED2 : 14;       //!< [31:18] Reserved
    } B;
} hw_ddr_cr01_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR01 register
 */
//@{
#define HW_DDR_CR01_ADDR         (REGS_DDR_BASE + 0x4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR01              (*(__I hw_ddr_cr01_t *) HW_DDR_CR01_ADDR)
#define HW_DDR_CR01_RD()         (HW_DDR_CR01.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR01 bitfields
 */

/*!
 * @name Register DDR_CR01, field MAXROW[4:0] (RO)
 *
 * Maximum width of the memory address bus. This field always reads 0x10. This
 * value can be used to set the CR25[ADDPINS] field, where: ADDPINS = MAXROW minus
 * number of row bits in the memory device.
 */
//@{
#define BP_DDR_CR01_MAXROW   (0U)          //!< Bit position for DDR_CR01_MAXROW.
#define BM_DDR_CR01_MAXROW   (0x0000001FU) //!< Bit mask for DDR_CR01_MAXROW.
#define BS_DDR_CR01_MAXROW   (5U)          //!< Bit field size in bits for DDR_CR01_MAXROW.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR01_MAXROW field.
#define BR_DDR_CR01_MAXROW   (HW_DDR_CR01.B.MAXROW)
#endif
//@}

/*!
 * @name Register DDR_CR01, field MAXCOL[11:8] (RO)
 *
 * Maximum width of the column address in the DRAM devices. This value can be
 * used to set the CR25[COLSIZ] field, where: COLSIZ = MAXCOL minus number of
 * column bits in the memory device
 *
 * Values:
 * - 0000 - 0
 * - 0001 - 1
 * - 1011 - 11
 * - 1100 - Reserved
 * - 1101 - Reserved
 * - 1110 - Reserved
 * - 1111 - Reserved
 */
//@{
#define BP_DDR_CR01_MAXCOL   (8U)          //!< Bit position for DDR_CR01_MAXCOL.
#define BM_DDR_CR01_MAXCOL   (0x00000F00U) //!< Bit mask for DDR_CR01_MAXCOL.
#define BS_DDR_CR01_MAXCOL   (4U)          //!< Bit field size in bits for DDR_CR01_MAXCOL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR01_MAXCOL field.
#define BR_DDR_CR01_MAXCOL   (HW_DDR_CR01.B.MAXCOL)
#endif
//@}

/*!
 * @name Register DDR_CR01, field CSMAX[17:16] (RO)
 *
 * Maximum number of chip selects supported by the memory controller. This field
 * may not necessarily indicate how many chip selects are available externally
 * on this device.
 *
 * Values:
 * - 00 - Zero
 * - 01 - One
 * - 10 - Two
 * - 11 - Reserved
 */
//@{
#define BP_DDR_CR01_CSMAX    (16U)         //!< Bit position for DDR_CR01_CSMAX.
#define BM_DDR_CR01_CSMAX    (0x00030000U) //!< Bit mask for DDR_CR01_CSMAX.
#define BS_DDR_CR01_CSMAX    (2U)          //!< Bit field size in bits for DDR_CR01_CSMAX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR01_CSMAX field.
#define BR_DDR_CR01_CSMAX    (HW_DDR_CR01.B.CSMAX)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR02 - DDR Control Register 2
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR02 - DDR Control Register 2 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr02
{
    uint32_t U;
    struct _hw_ddr_cr02_bitfields
    {
        uint32_t TINIT : 24;           //!< [23:0] Time Initialization
        uint32_t INITAREF : 4;         //!< [27:24] Initialization Auto-Refresh
        uint32_t RESERVED0 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr02_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR02 register
 */
//@{
#define HW_DDR_CR02_ADDR         (REGS_DDR_BASE + 0x8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR02              (*(__IO hw_ddr_cr02_t *) HW_DDR_CR02_ADDR)
#define HW_DDR_CR02_RD()         (HW_DDR_CR02.U)
#define HW_DDR_CR02_WR(v)        (HW_DDR_CR02.U = (v))
#define HW_DDR_CR02_SET(v)       (HW_DDR_CR02_WR(HW_DDR_CR02_RD() |  (v)))
#define HW_DDR_CR02_CLR(v)       (HW_DDR_CR02_WR(HW_DDR_CR02_RD() & ~(v)))
#define HW_DDR_CR02_TOG(v)       (HW_DDR_CR02_WR(HW_DDR_CR02_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR02 bitfields
 */

/*!
 * @name Register DDR_CR02, field TINIT[23:0] (RW)
 *
 * Defines the DRAM initialization time in cycles.
 */
//@{
#define BP_DDR_CR02_TINIT    (0U)          //!< Bit position for DDR_CR02_TINIT.
#define BM_DDR_CR02_TINIT    (0x00FFFFFFU) //!< Bit mask for DDR_CR02_TINIT.
#define BS_DDR_CR02_TINIT    (24U)         //!< Bit field size in bits for DDR_CR02_TINIT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR02_TINIT field.
#define BR_DDR_CR02_TINIT    (HW_DDR_CR02.B.TINIT)
#endif

//! @brief Format value for bitfield DDR_CR02_TINIT.
#define BF_DDR_CR02_TINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR02_TINIT), uint32_t) & BM_DDR_CR02_TINIT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TINIT field to a new value.
#define BW_DDR_CR02_TINIT(v) (HW_DDR_CR02_WR((HW_DDR_CR02_RD() & ~BM_DDR_CR02_TINIT) | BF_DDR_CR02_TINIT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR02, field INITAREF[27:24] (RW)
 *
 * Number of auto-refresh commands to execute during DRAM initialization.
 */
//@{
#define BP_DDR_CR02_INITAREF (24U)         //!< Bit position for DDR_CR02_INITAREF.
#define BM_DDR_CR02_INITAREF (0x0F000000U) //!< Bit mask for DDR_CR02_INITAREF.
#define BS_DDR_CR02_INITAREF (4U)          //!< Bit field size in bits for DDR_CR02_INITAREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR02_INITAREF field.
#define BR_DDR_CR02_INITAREF (HW_DDR_CR02.B.INITAREF)
#endif

//! @brief Format value for bitfield DDR_CR02_INITAREF.
#define BF_DDR_CR02_INITAREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR02_INITAREF), uint32_t) & BM_DDR_CR02_INITAREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the INITAREF field to a new value.
#define BW_DDR_CR02_INITAREF(v) (HW_DDR_CR02_WR((HW_DDR_CR02_RD() & ~BM_DDR_CR02_INITAREF) | BF_DDR_CR02_INITAREF(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR03 - DDR Control Register 3
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR03 - DDR Control Register 3 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr03
{
    uint32_t U;
    struct _hw_ddr_cr03_bitfields
    {
        uint32_t LATLIN : 4;           //!< [3:0] Latency Linear
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t LATGATE : 4;          //!< [11:8] Latency Gate
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t WRLAT : 4;            //!< [19:16] Write Latency
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t TCCD : 5;             //!< [28:24] Time CAS-to-CAS Delay
        uint32_t RESERVED3 : 3;        //!< [31:29] Reserved
    } B;
} hw_ddr_cr03_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR03 register
 */
//@{
#define HW_DDR_CR03_ADDR         (REGS_DDR_BASE + 0xCU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR03              (*(__IO hw_ddr_cr03_t *) HW_DDR_CR03_ADDR)
#define HW_DDR_CR03_RD()         (HW_DDR_CR03.U)
#define HW_DDR_CR03_WR(v)        (HW_DDR_CR03.U = (v))
#define HW_DDR_CR03_SET(v)       (HW_DDR_CR03_WR(HW_DDR_CR03_RD() |  (v)))
#define HW_DDR_CR03_CLR(v)       (HW_DDR_CR03_WR(HW_DDR_CR03_RD() & ~(v)))
#define HW_DDR_CR03_TOG(v)       (HW_DDR_CR03_WR(HW_DDR_CR03_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR03 bitfields
 */

/*!
 * @name Register DDR_CR03, field LATLIN[3:0] (RW)
 *
 * Sets the CAS latency linear value in half cycle increments. This sets an
 * internal adjustment for the delay from when the read command is sent from the
 * memory controller to when data is received back. The window of time in which the
 * data is captured is a fixed length. This field adjusts the start of this data
 * capture window. Not all linear values are supported for the memory devices
 * being used. Refer to the device's data sheet for valid values.
 *
 * Values:
 * - 0000 - Reserved
 * - 0001 - Reserved
 * - 0010 - 1 cycle
 * - 0011 - 1.5 cycles
 * - 1111 - 7.5 cycles
 */
//@{
#define BP_DDR_CR03_LATLIN   (0U)          //!< Bit position for DDR_CR03_LATLIN.
#define BM_DDR_CR03_LATLIN   (0x0000000FU) //!< Bit mask for DDR_CR03_LATLIN.
#define BS_DDR_CR03_LATLIN   (4U)          //!< Bit field size in bits for DDR_CR03_LATLIN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR03_LATLIN field.
#define BR_DDR_CR03_LATLIN   (HW_DDR_CR03.B.LATLIN)
#endif

//! @brief Format value for bitfield DDR_CR03_LATLIN.
#define BF_DDR_CR03_LATLIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR03_LATLIN), uint32_t) & BM_DDR_CR03_LATLIN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LATLIN field to a new value.
#define BW_DDR_CR03_LATLIN(v) (HW_DDR_CR03_WR((HW_DDR_CR03_RD() & ~BM_DDR_CR03_LATLIN) | BF_DDR_CR03_LATLIN(v)))
#endif
//@}

/*!
 * @name Register DDR_CR03, field LATGATE[11:8] (RW)
 *
 * Adjusts data capture gate open time by half cycles. This parameter is
 * programmed differently than LATLIN field when there are fixed offsets in the flight
 * path between the memories and the memory controller for clock gating. When this
 * field is larger than LATLIN, the data capture window becomes shorter. A value
 * smaller than LATLIN may have no effect on the data capture window, depending
 * on the fixed offsets in the ASIC and the board.
 */
//@{
#define BP_DDR_CR03_LATGATE  (8U)          //!< Bit position for DDR_CR03_LATGATE.
#define BM_DDR_CR03_LATGATE  (0x00000F00U) //!< Bit mask for DDR_CR03_LATGATE.
#define BS_DDR_CR03_LATGATE  (4U)          //!< Bit field size in bits for DDR_CR03_LATGATE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR03_LATGATE field.
#define BR_DDR_CR03_LATGATE  (HW_DDR_CR03.B.LATGATE)
#endif

//! @brief Format value for bitfield DDR_CR03_LATGATE.
#define BF_DDR_CR03_LATGATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR03_LATGATE), uint32_t) & BM_DDR_CR03_LATGATE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LATGATE field to a new value.
#define BW_DDR_CR03_LATGATE(v) (HW_DDR_CR03_WR((HW_DDR_CR03_RD() & ~BM_DDR_CR03_LATGATE) | BF_DDR_CR03_LATGATE(v)))
#endif
//@}

/*!
 * @name Register DDR_CR03, field WRLAT[19:16] (RW)
 *
 * Defines the DRAM write latency (WRLAT) when the write command is issued to
 * the time the write data is presented to the DRAM devices in cycles. This
 * parameter must be set to 0x1 when the memory controller is in DDR1 mode.
 */
//@{
#define BP_DDR_CR03_WRLAT    (16U)         //!< Bit position for DDR_CR03_WRLAT.
#define BM_DDR_CR03_WRLAT    (0x000F0000U) //!< Bit mask for DDR_CR03_WRLAT.
#define BS_DDR_CR03_WRLAT    (4U)          //!< Bit field size in bits for DDR_CR03_WRLAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR03_WRLAT field.
#define BR_DDR_CR03_WRLAT    (HW_DDR_CR03.B.WRLAT)
#endif

//! @brief Format value for bitfield DDR_CR03_WRLAT.
#define BF_DDR_CR03_WRLAT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR03_WRLAT), uint32_t) & BM_DDR_CR03_WRLAT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRLAT field to a new value.
#define BW_DDR_CR03_WRLAT(v) (HW_DDR_CR03_WR((HW_DDR_CR03_RD() & ~BM_DDR_CR03_WRLAT) | BF_DDR_CR03_WRLAT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR03, field TCCD[28:24] (RW)
 *
 * DRAM CAS-to-CAS parameter in cycles.
 */
//@{
#define BP_DDR_CR03_TCCD     (24U)         //!< Bit position for DDR_CR03_TCCD.
#define BM_DDR_CR03_TCCD     (0x1F000000U) //!< Bit mask for DDR_CR03_TCCD.
#define BS_DDR_CR03_TCCD     (5U)          //!< Bit field size in bits for DDR_CR03_TCCD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR03_TCCD field.
#define BR_DDR_CR03_TCCD     (HW_DDR_CR03.B.TCCD)
#endif

//! @brief Format value for bitfield DDR_CR03_TCCD.
#define BF_DDR_CR03_TCCD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR03_TCCD), uint32_t) & BM_DDR_CR03_TCCD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TCCD field to a new value.
#define BW_DDR_CR03_TCCD(v)  (HW_DDR_CR03_WR((HW_DDR_CR03_RD() & ~BM_DDR_CR03_TCCD) | BF_DDR_CR03_TCCD(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR04 - DDR Control Register 4
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR04 - DDR Control Register 4 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr04
{
    uint32_t U;
    struct _hw_ddr_cr04_bitfields
    {
        uint32_t TBINT : 3;            //!< [2:0] Time Burst Interrupt Interval
        uint32_t RESERVED0 : 5;        //!< [7:3] Reserved
        uint32_t TRRD : 3;             //!< [10:8]
        uint32_t RESERVED1 : 5;        //!< [15:11] Reserved
        uint32_t TRC : 6;              //!< [21:16]
        uint32_t RESERVED2 : 2;        //!< [23:22] Reserved
        uint32_t TRASMIN : 8;          //!< [31:24] Time RAS Minimum
    } B;
} hw_ddr_cr04_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR04 register
 */
//@{
#define HW_DDR_CR04_ADDR         (REGS_DDR_BASE + 0x10U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR04              (*(__IO hw_ddr_cr04_t *) HW_DDR_CR04_ADDR)
#define HW_DDR_CR04_RD()         (HW_DDR_CR04.U)
#define HW_DDR_CR04_WR(v)        (HW_DDR_CR04.U = (v))
#define HW_DDR_CR04_SET(v)       (HW_DDR_CR04_WR(HW_DDR_CR04_RD() |  (v)))
#define HW_DDR_CR04_CLR(v)       (HW_DDR_CR04_WR(HW_DDR_CR04_RD() & ~(v)))
#define HW_DDR_CR04_TOG(v)       (HW_DDR_CR04_WR(HW_DDR_CR04_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR04 bitfields
 */

/*!
 * @name Register DDR_CR04, field TBINT[2:0] (RW)
 *
 * DRAM burst interrupt interval in cycles.
 */
//@{
#define BP_DDR_CR04_TBINT    (0U)          //!< Bit position for DDR_CR04_TBINT.
#define BM_DDR_CR04_TBINT    (0x00000007U) //!< Bit mask for DDR_CR04_TBINT.
#define BS_DDR_CR04_TBINT    (3U)          //!< Bit field size in bits for DDR_CR04_TBINT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR04_TBINT field.
#define BR_DDR_CR04_TBINT    (HW_DDR_CR04.B.TBINT)
#endif

//! @brief Format value for bitfield DDR_CR04_TBINT.
#define BF_DDR_CR04_TBINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR04_TBINT), uint32_t) & BM_DDR_CR04_TBINT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TBINT field to a new value.
#define BW_DDR_CR04_TBINT(v) (HW_DDR_CR04_WR((HW_DDR_CR04_RD() & ~BM_DDR_CR04_TBINT) | BF_DDR_CR04_TBINT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR04, field TRRD[10:8] (RW)
 *
 * Defines the DRAM activate-to-activate delay for different banks (TRRD) in
 * cycles.
 */
//@{
#define BP_DDR_CR04_TRRD     (8U)          //!< Bit position for DDR_CR04_TRRD.
#define BM_DDR_CR04_TRRD     (0x00000700U) //!< Bit mask for DDR_CR04_TRRD.
#define BS_DDR_CR04_TRRD     (3U)          //!< Bit field size in bits for DDR_CR04_TRRD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR04_TRRD field.
#define BR_DDR_CR04_TRRD     (HW_DDR_CR04.B.TRRD)
#endif

//! @brief Format value for bitfield DDR_CR04_TRRD.
#define BF_DDR_CR04_TRRD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR04_TRRD), uint32_t) & BM_DDR_CR04_TRRD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRRD field to a new value.
#define BW_DDR_CR04_TRRD(v)  (HW_DDR_CR04_WR((HW_DDR_CR04_RD() & ~BM_DDR_CR04_TRRD) | BF_DDR_CR04_TRRD(v)))
#endif
//@}

/*!
 * @name Register DDR_CR04, field TRC[21:16] (RW)
 *
 * Defines the DRAM period between active commands for the same bank (TRC) in
 * cycles.
 */
//@{
#define BP_DDR_CR04_TRC      (16U)         //!< Bit position for DDR_CR04_TRC.
#define BM_DDR_CR04_TRC      (0x003F0000U) //!< Bit mask for DDR_CR04_TRC.
#define BS_DDR_CR04_TRC      (6U)          //!< Bit field size in bits for DDR_CR04_TRC.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR04_TRC field.
#define BR_DDR_CR04_TRC      (HW_DDR_CR04.B.TRC)
#endif

//! @brief Format value for bitfield DDR_CR04_TRC.
#define BF_DDR_CR04_TRC(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR04_TRC), uint32_t) & BM_DDR_CR04_TRC)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRC field to a new value.
#define BW_DDR_CR04_TRC(v)   (HW_DDR_CR04_WR((HW_DDR_CR04_RD() & ~BM_DDR_CR04_TRC) | BF_DDR_CR04_TRC(v)))
#endif
//@}

/*!
 * @name Register DDR_CR04, field TRASMIN[31:24] (RW)
 *
 * Defines the DRAM minimum row active time (TRAS_MIN) in cycles.
 */
//@{
#define BP_DDR_CR04_TRASMIN  (24U)         //!< Bit position for DDR_CR04_TRASMIN.
#define BM_DDR_CR04_TRASMIN  (0xFF000000U) //!< Bit mask for DDR_CR04_TRASMIN.
#define BS_DDR_CR04_TRASMIN  (8U)          //!< Bit field size in bits for DDR_CR04_TRASMIN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR04_TRASMIN field.
#define BR_DDR_CR04_TRASMIN  (HW_DDR_CR04.B.TRASMIN)
#endif

//! @brief Format value for bitfield DDR_CR04_TRASMIN.
#define BF_DDR_CR04_TRASMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR04_TRASMIN), uint32_t) & BM_DDR_CR04_TRASMIN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRASMIN field to a new value.
#define BW_DDR_CR04_TRASMIN(v) (HW_DDR_CR04_WR((HW_DDR_CR04_RD() & ~BM_DDR_CR04_TRASMIN) | BF_DDR_CR04_TRASMIN(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR05 - DDR Control Register 5
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR05 - DDR Control Register 5 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr05
{
    uint32_t U;
    struct _hw_ddr_cr05_bitfields
    {
        uint32_t TWTR : 4;             //!< [3:0] Time Write-To-Read
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t TRP : 4;              //!< [11:8]
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t TRTP : 3;             //!< [18:16] Time Read-To-Precharge
        uint32_t RESERVED2 : 5;        //!< [23:19] Reserved
        uint32_t TMRD : 5;             //!< [28:24]
        uint32_t RESERVED3 : 3;        //!< [31:29] Reserved
    } B;
} hw_ddr_cr05_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR05 register
 */
//@{
#define HW_DDR_CR05_ADDR         (REGS_DDR_BASE + 0x14U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR05              (*(__IO hw_ddr_cr05_t *) HW_DDR_CR05_ADDR)
#define HW_DDR_CR05_RD()         (HW_DDR_CR05.U)
#define HW_DDR_CR05_WR(v)        (HW_DDR_CR05.U = (v))
#define HW_DDR_CR05_SET(v)       (HW_DDR_CR05_WR(HW_DDR_CR05_RD() |  (v)))
#define HW_DDR_CR05_CLR(v)       (HW_DDR_CR05_WR(HW_DDR_CR05_RD() & ~(v)))
#define HW_DDR_CR05_TOG(v)       (HW_DDR_CR05_WR(HW_DDR_CR05_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR05 bitfields
 */

/*!
 * @name Register DDR_CR05, field TWTR[3:0] (RW)
 *
 * Sets the number of cycles needed to switch from a write to a read operation,
 * as dictated by the DDR SDRAM specification.
 */
//@{
#define BP_DDR_CR05_TWTR     (0U)          //!< Bit position for DDR_CR05_TWTR.
#define BM_DDR_CR05_TWTR     (0x0000000FU) //!< Bit mask for DDR_CR05_TWTR.
#define BS_DDR_CR05_TWTR     (4U)          //!< Bit field size in bits for DDR_CR05_TWTR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR05_TWTR field.
#define BR_DDR_CR05_TWTR     (HW_DDR_CR05.B.TWTR)
#endif

//! @brief Format value for bitfield DDR_CR05_TWTR.
#define BF_DDR_CR05_TWTR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR05_TWTR), uint32_t) & BM_DDR_CR05_TWTR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TWTR field to a new value.
#define BW_DDR_CR05_TWTR(v)  (HW_DDR_CR05_WR((HW_DDR_CR05_RD() & ~BM_DDR_CR05_TWTR) | BF_DDR_CR05_TWTR(v)))
#endif
//@}

/*!
 * @name Register DDR_CR05, field TRP[11:8] (RW)
 *
 * Defines the DRAM precharge command time (TRP) in cycles.
 */
//@{
#define BP_DDR_CR05_TRP      (8U)          //!< Bit position for DDR_CR05_TRP.
#define BM_DDR_CR05_TRP      (0x00000F00U) //!< Bit mask for DDR_CR05_TRP.
#define BS_DDR_CR05_TRP      (4U)          //!< Bit field size in bits for DDR_CR05_TRP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR05_TRP field.
#define BR_DDR_CR05_TRP      (HW_DDR_CR05.B.TRP)
#endif

//! @brief Format value for bitfield DDR_CR05_TRP.
#define BF_DDR_CR05_TRP(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR05_TRP), uint32_t) & BM_DDR_CR05_TRP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRP field to a new value.
#define BW_DDR_CR05_TRP(v)   (HW_DDR_CR05_WR((HW_DDR_CR05_RD() & ~BM_DDR_CR05_TRP) | BF_DDR_CR05_TRP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR05, field TRTP[18:16] (RW)
 *
 * Defines the DRAM read to precharge time (TRTP) in cycles.
 */
//@{
#define BP_DDR_CR05_TRTP     (16U)         //!< Bit position for DDR_CR05_TRTP.
#define BM_DDR_CR05_TRTP     (0x00070000U) //!< Bit mask for DDR_CR05_TRTP.
#define BS_DDR_CR05_TRTP     (3U)          //!< Bit field size in bits for DDR_CR05_TRTP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR05_TRTP field.
#define BR_DDR_CR05_TRTP     (HW_DDR_CR05.B.TRTP)
#endif

//! @brief Format value for bitfield DDR_CR05_TRTP.
#define BF_DDR_CR05_TRTP(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR05_TRTP), uint32_t) & BM_DDR_CR05_TRTP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRTP field to a new value.
#define BW_DDR_CR05_TRTP(v)  (HW_DDR_CR05_WR((HW_DDR_CR05_RD() & ~BM_DDR_CR05_TRTP) | BF_DDR_CR05_TRTP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR05, field TMRD[28:24] (RW)
 *
 * DRAM TMRD parameter in cycles.
 */
//@{
#define BP_DDR_CR05_TMRD     (24U)         //!< Bit position for DDR_CR05_TMRD.
#define BM_DDR_CR05_TMRD     (0x1F000000U) //!< Bit mask for DDR_CR05_TMRD.
#define BS_DDR_CR05_TMRD     (5U)          //!< Bit field size in bits for DDR_CR05_TMRD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR05_TMRD field.
#define BR_DDR_CR05_TMRD     (HW_DDR_CR05.B.TMRD)
#endif

//! @brief Format value for bitfield DDR_CR05_TMRD.
#define BF_DDR_CR05_TMRD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR05_TMRD), uint32_t) & BM_DDR_CR05_TMRD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TMRD field to a new value.
#define BW_DDR_CR05_TMRD(v)  (HW_DDR_CR05_WR((HW_DDR_CR05_RD() & ~BM_DDR_CR05_TMRD) | BF_DDR_CR05_TMRD(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR06 - DDR Control Register 6
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR06 - DDR Control Register 6 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr06
{
    uint32_t U;
    struct _hw_ddr_cr06_bitfields
    {
        uint32_t TMOD : 8;             //!< [7:0] Time Mode
        uint32_t TRASMAX : 16;         //!< [23:8] Time Row Access Maximum
        uint32_t INTWBR : 1;           //!< [24] Interrupt Write Burst
        uint32_t RESERVED0 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr06_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR06 register
 */
//@{
#define HW_DDR_CR06_ADDR         (REGS_DDR_BASE + 0x18U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR06              (*(__IO hw_ddr_cr06_t *) HW_DDR_CR06_ADDR)
#define HW_DDR_CR06_RD()         (HW_DDR_CR06.U)
#define HW_DDR_CR06_WR(v)        (HW_DDR_CR06.U = (v))
#define HW_DDR_CR06_SET(v)       (HW_DDR_CR06_WR(HW_DDR_CR06_RD() |  (v)))
#define HW_DDR_CR06_CLR(v)       (HW_DDR_CR06_WR(HW_DDR_CR06_RD() & ~(v)))
#define HW_DDR_CR06_TOG(v)       (HW_DDR_CR06_WR(HW_DDR_CR06_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR06 bitfields
 */

/*!
 * @name Register DDR_CR06, field TMOD[7:0] (RW)
 *
 * Defines the number of cycles of wait time between mode commands. For write
 * leveling, this is defined as the number of cycles of wait time after a MRS
 * command to the ODT enable.
 */
//@{
#define BP_DDR_CR06_TMOD     (0U)          //!< Bit position for DDR_CR06_TMOD.
#define BM_DDR_CR06_TMOD     (0x000000FFU) //!< Bit mask for DDR_CR06_TMOD.
#define BS_DDR_CR06_TMOD     (8U)          //!< Bit field size in bits for DDR_CR06_TMOD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR06_TMOD field.
#define BR_DDR_CR06_TMOD     (HW_DDR_CR06.B.TMOD)
#endif

//! @brief Format value for bitfield DDR_CR06_TMOD.
#define BF_DDR_CR06_TMOD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR06_TMOD), uint32_t) & BM_DDR_CR06_TMOD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TMOD field to a new value.
#define BW_DDR_CR06_TMOD(v)  (HW_DDR_CR06_WR((HW_DDR_CR06_RD() & ~BM_DDR_CR06_TMOD) | BF_DDR_CR06_TMOD(v)))
#endif
//@}

/*!
 * @name Register DDR_CR06, field TRASMAX[23:8] (RW)
 *
 * Defines the DRAM maximum row active time (TRAS_MAX) in cycles.
 */
//@{
#define BP_DDR_CR06_TRASMAX  (8U)          //!< Bit position for DDR_CR06_TRASMAX.
#define BM_DDR_CR06_TRASMAX  (0x00FFFF00U) //!< Bit mask for DDR_CR06_TRASMAX.
#define BS_DDR_CR06_TRASMAX  (16U)         //!< Bit field size in bits for DDR_CR06_TRASMAX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR06_TRASMAX field.
#define BR_DDR_CR06_TRASMAX  (HW_DDR_CR06.B.TRASMAX)
#endif

//! @brief Format value for bitfield DDR_CR06_TRASMAX.
#define BF_DDR_CR06_TRASMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR06_TRASMAX), uint32_t) & BM_DDR_CR06_TRASMAX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRASMAX field to a new value.
#define BW_DDR_CR06_TRASMAX(v) (HW_DDR_CR06_WR((HW_DDR_CR06_RD() & ~BM_DDR_CR06_TRASMAX) | BF_DDR_CR06_TRASMAX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR06, field INTWBR[24] (RW)
 *
 * Allows the controller to interrupt a write burst to the DRAMs with a read
 * command. Some memory devices do not support this functionality.
 *
 * Values:
 * - 0 - Read commands cannot interrupt write commands
 * - 1 - Read commands can interrupt write commands
 */
//@{
#define BP_DDR_CR06_INTWBR   (24U)         //!< Bit position for DDR_CR06_INTWBR.
#define BM_DDR_CR06_INTWBR   (0x01000000U) //!< Bit mask for DDR_CR06_INTWBR.
#define BS_DDR_CR06_INTWBR   (1U)          //!< Bit field size in bits for DDR_CR06_INTWBR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR06_INTWBR field.
#define BR_DDR_CR06_INTWBR   (BITBAND_ACCESS32(HW_DDR_CR06_ADDR, BP_DDR_CR06_INTWBR))
#endif

//! @brief Format value for bitfield DDR_CR06_INTWBR.
#define BF_DDR_CR06_INTWBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR06_INTWBR), uint32_t) & BM_DDR_CR06_INTWBR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the INTWBR field to a new value.
#define BW_DDR_CR06_INTWBR(v) (BITBAND_ACCESS32(HW_DDR_CR06_ADDR, BP_DDR_CR06_INTWBR) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR07 - DDR Control Register 7
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR07 - DDR Control Register 7 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr07
{
    uint32_t U;
    struct _hw_ddr_cr07_bitfields
    {
        uint32_t CLKPW : 3;            //!< [2:0] Clock Pulse Width
        uint32_t RESERVED0 : 5;        //!< [7:3] Reserved
        uint32_t TCKESR : 5;           //!< [12:8] Time Clock low Self Refresh
        uint32_t RESERVED1 : 3;        //!< [15:13] Reserved
        uint32_t AP : 1;               //!< [16] Auto Precharge
        uint32_t RESERVED2 : 7;        //!< [23:17] Reserved
        uint32_t CCAPEN : 1;           //!< [24] Concurrent Auto-Precharge Enable
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr07_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR07 register
 */
//@{
#define HW_DDR_CR07_ADDR         (REGS_DDR_BASE + 0x1CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR07              (*(__IO hw_ddr_cr07_t *) HW_DDR_CR07_ADDR)
#define HW_DDR_CR07_RD()         (HW_DDR_CR07.U)
#define HW_DDR_CR07_WR(v)        (HW_DDR_CR07.U = (v))
#define HW_DDR_CR07_SET(v)       (HW_DDR_CR07_WR(HW_DDR_CR07_RD() |  (v)))
#define HW_DDR_CR07_CLR(v)       (HW_DDR_CR07_WR(HW_DDR_CR07_RD() & ~(v)))
#define HW_DDR_CR07_TOG(v)       (HW_DDR_CR07_WR(HW_DDR_CR07_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR07 bitfields
 */

/*!
 * @name Register DDR_CR07, field CLKPW[2:0] (RW)
 *
 * Minimum CLK pulse width in cycles.
 */
//@{
#define BP_DDR_CR07_CLKPW    (0U)          //!< Bit position for DDR_CR07_CLKPW.
#define BM_DDR_CR07_CLKPW    (0x00000007U) //!< Bit mask for DDR_CR07_CLKPW.
#define BS_DDR_CR07_CLKPW    (3U)          //!< Bit field size in bits for DDR_CR07_CLKPW.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR07_CLKPW field.
#define BR_DDR_CR07_CLKPW    (HW_DDR_CR07.B.CLKPW)
#endif

//! @brief Format value for bitfield DDR_CR07_CLKPW.
#define BF_DDR_CR07_CLKPW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR07_CLKPW), uint32_t) & BM_DDR_CR07_CLKPW)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKPW field to a new value.
#define BW_DDR_CR07_CLKPW(v) (HW_DDR_CR07_WR((HW_DDR_CR07_RD() & ~BM_DDR_CR07_CLKPW) | BF_DDR_CR07_CLKPW(v)))
#endif
//@}

/*!
 * @name Register DDR_CR07, field TCKESR[12:8] (RW)
 *
 * Minimum CLK low pulse width during self-refresh.
 */
//@{
#define BP_DDR_CR07_TCKESR   (8U)          //!< Bit position for DDR_CR07_TCKESR.
#define BM_DDR_CR07_TCKESR   (0x00001F00U) //!< Bit mask for DDR_CR07_TCKESR.
#define BS_DDR_CR07_TCKESR   (5U)          //!< Bit field size in bits for DDR_CR07_TCKESR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR07_TCKESR field.
#define BR_DDR_CR07_TCKESR   (HW_DDR_CR07.B.TCKESR)
#endif

//! @brief Format value for bitfield DDR_CR07_TCKESR.
#define BF_DDR_CR07_TCKESR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR07_TCKESR), uint32_t) & BM_DDR_CR07_TCKESR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TCKESR field to a new value.
#define BW_DDR_CR07_TCKESR(v) (HW_DDR_CR07_WR((HW_DDR_CR07_RD() & ~BM_DDR_CR07_TCKESR) | BF_DDR_CR07_TCKESR(v)))
#endif
//@}

/*!
 * @name Register DDR_CR07, field AP[16] (RW)
 *
 * Enables auto pre-charge mode of the memory controller.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR07_AP       (16U)         //!< Bit position for DDR_CR07_AP.
#define BM_DDR_CR07_AP       (0x00010000U) //!< Bit mask for DDR_CR07_AP.
#define BS_DDR_CR07_AP       (1U)          //!< Bit field size in bits for DDR_CR07_AP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR07_AP field.
#define BR_DDR_CR07_AP       (BITBAND_ACCESS32(HW_DDR_CR07_ADDR, BP_DDR_CR07_AP))
#endif

//! @brief Format value for bitfield DDR_CR07_AP.
#define BF_DDR_CR07_AP(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR07_AP), uint32_t) & BM_DDR_CR07_AP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AP field to a new value.
#define BW_DDR_CR07_AP(v)    (BITBAND_ACCESS32(HW_DDR_CR07_ADDR, BP_DDR_CR07_AP) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR07, field CCAPEN[24] (RW)
 *
 * Allows controller to issue commands to other banks while a bank is in auto
 * precharge. Some DRAM devices do not allow one bank to auto pre-charge while
 * another bank is reading or writing. The JEDEC standard allows concurrent auto
 * pre-charge. Set this parameter for the DRAM device being used.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR07_CCAPEN   (24U)         //!< Bit position for DDR_CR07_CCAPEN.
#define BM_DDR_CR07_CCAPEN   (0x01000000U) //!< Bit mask for DDR_CR07_CCAPEN.
#define BS_DDR_CR07_CCAPEN   (1U)          //!< Bit field size in bits for DDR_CR07_CCAPEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR07_CCAPEN field.
#define BR_DDR_CR07_CCAPEN   (BITBAND_ACCESS32(HW_DDR_CR07_ADDR, BP_DDR_CR07_CCAPEN))
#endif

//! @brief Format value for bitfield DDR_CR07_CCAPEN.
#define BF_DDR_CR07_CCAPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR07_CCAPEN), uint32_t) & BM_DDR_CR07_CCAPEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CCAPEN field to a new value.
#define BW_DDR_CR07_CCAPEN(v) (BITBAND_ACCESS32(HW_DDR_CR07_ADDR, BP_DDR_CR07_CCAPEN) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR08 - DDR Control Register 8
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR08 - DDR Control Register 8 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr08
{
    uint32_t U;
    struct _hw_ddr_cr08_bitfields
    {
        uint32_t TRAS : 1;             //!< [0] Time RAS lockout
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t TRASDI : 8;           //!< [15:8] Time RAS-to-CAS Delay Interval
        uint32_t TWR : 5;              //!< [20:16] Time Write Recovery
        uint32_t RESERVED1 : 3;        //!< [23:21] Reserved
        uint32_t TDAL : 5;             //!< [28:24]
        uint32_t RESERVED2 : 3;        //!< [31:29] Reserved
    } B;
} hw_ddr_cr08_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR08 register
 */
//@{
#define HW_DDR_CR08_ADDR         (REGS_DDR_BASE + 0x20U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR08              (*(__IO hw_ddr_cr08_t *) HW_DDR_CR08_ADDR)
#define HW_DDR_CR08_RD()         (HW_DDR_CR08.U)
#define HW_DDR_CR08_WR(v)        (HW_DDR_CR08.U = (v))
#define HW_DDR_CR08_SET(v)       (HW_DDR_CR08_WR(HW_DDR_CR08_RD() |  (v)))
#define HW_DDR_CR08_CLR(v)       (HW_DDR_CR08_WR(HW_DDR_CR08_RD() & ~(v)))
#define HW_DDR_CR08_TOG(v)       (HW_DDR_CR08_WR(HW_DDR_CR08_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR08 bitfields
 */

/*!
 * @name Register DDR_CR08, field TRAS[0] (RW)
 *
 * Defines the t RAS lockout setting for the DRAM device. t RAS lockout allows
 * the memory controller to execute auto pre-charge commands before the TRAS_MIN
 * parameter expires. 0 t RAS lockout not supported by memory device 1 t RAS
 * lockout supported by memory device
 */
//@{
#define BP_DDR_CR08_TRAS     (0U)          //!< Bit position for DDR_CR08_TRAS.
#define BM_DDR_CR08_TRAS     (0x00000001U) //!< Bit mask for DDR_CR08_TRAS.
#define BS_DDR_CR08_TRAS     (1U)          //!< Bit field size in bits for DDR_CR08_TRAS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR08_TRAS field.
#define BR_DDR_CR08_TRAS     (BITBAND_ACCESS32(HW_DDR_CR08_ADDR, BP_DDR_CR08_TRAS))
#endif

//! @brief Format value for bitfield DDR_CR08_TRAS.
#define BF_DDR_CR08_TRAS(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR08_TRAS), uint32_t) & BM_DDR_CR08_TRAS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRAS field to a new value.
#define BW_DDR_CR08_TRAS(v)  (BITBAND_ACCESS32(HW_DDR_CR08_ADDR, BP_DDR_CR08_TRAS) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR08, field TRASDI[15:8] (RW)
 *
 * Defines the DRAM RAS-to-CAS delay in cycles.
 */
//@{
#define BP_DDR_CR08_TRASDI   (8U)          //!< Bit position for DDR_CR08_TRASDI.
#define BM_DDR_CR08_TRASDI   (0x0000FF00U) //!< Bit mask for DDR_CR08_TRASDI.
#define BS_DDR_CR08_TRASDI   (8U)          //!< Bit field size in bits for DDR_CR08_TRASDI.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR08_TRASDI field.
#define BR_DDR_CR08_TRASDI   (HW_DDR_CR08.B.TRASDI)
#endif

//! @brief Format value for bitfield DDR_CR08_TRASDI.
#define BF_DDR_CR08_TRASDI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR08_TRASDI), uint32_t) & BM_DDR_CR08_TRASDI)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRASDI field to a new value.
#define BW_DDR_CR08_TRASDI(v) (HW_DDR_CR08_WR((HW_DDR_CR08_RD() & ~BM_DDR_CR08_TRASDI) | BF_DDR_CR08_TRASDI(v)))
#endif
//@}

/*!
 * @name Register DDR_CR08, field TWR[20:16] (RW)
 *
 * Defines the DRAM write recovery time (TWR) parameter in cycles.
 */
//@{
#define BP_DDR_CR08_TWR      (16U)         //!< Bit position for DDR_CR08_TWR.
#define BM_DDR_CR08_TWR      (0x001F0000U) //!< Bit mask for DDR_CR08_TWR.
#define BS_DDR_CR08_TWR      (5U)          //!< Bit field size in bits for DDR_CR08_TWR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR08_TWR field.
#define BR_DDR_CR08_TWR      (HW_DDR_CR08.B.TWR)
#endif

//! @brief Format value for bitfield DDR_CR08_TWR.
#define BF_DDR_CR08_TWR(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR08_TWR), uint32_t) & BM_DDR_CR08_TWR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TWR field to a new value.
#define BW_DDR_CR08_TWR(v)   (HW_DDR_CR08_WR((HW_DDR_CR08_RD() & ~BM_DDR_CR08_TWR) | BF_DDR_CR08_TWR(v)))
#endif
//@}

/*!
 * @name Register DDR_CR08, field TDAL[28:24] (RW)
 *
 * Defines the auto-precharge write recovery time when auto-precharge is enabled
 * (CR01[AP] is set), in cycles. This is defined internally as t RP (pre-charge
 * time) + auto-precharge write recovery time. Not all memories use this
 * parameter. If t DAL is defined in the memory specification, then program this
 * parameter to the specified value. If the memory does not specify a t DAL time, then
 * program this parameter to t WR + t RP . Do not program this parameter with a
 * value of 0x0. Else, the memory controller does not function properly when
 * auto-precharge is enabled.
 */
//@{
#define BP_DDR_CR08_TDAL     (24U)         //!< Bit position for DDR_CR08_TDAL.
#define BM_DDR_CR08_TDAL     (0x1F000000U) //!< Bit mask for DDR_CR08_TDAL.
#define BS_DDR_CR08_TDAL     (5U)          //!< Bit field size in bits for DDR_CR08_TDAL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR08_TDAL field.
#define BR_DDR_CR08_TDAL     (HW_DDR_CR08.B.TDAL)
#endif

//! @brief Format value for bitfield DDR_CR08_TDAL.
#define BF_DDR_CR08_TDAL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR08_TDAL), uint32_t) & BM_DDR_CR08_TDAL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TDAL field to a new value.
#define BW_DDR_CR08_TDAL(v)  (HW_DDR_CR08_WR((HW_DDR_CR08_RD() & ~BM_DDR_CR08_TDAL) | BF_DDR_CR08_TDAL(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR09 - DDR Control Register 9
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR09 - DDR Control Register 9 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr09
{
    uint32_t U;
    struct _hw_ddr_cr09_bitfields
    {
        uint32_t TDLL : 16;            //!< [15:0] Time DLL
        uint32_t NOCMD : 1;            //!< [16] No Command
        uint32_t RESERVED0 : 7;        //!< [23:17] Reserved
        uint32_t BSTLEN : 3;           //!< [26:24] Burst Length
        uint32_t RESERVED1 : 5;        //!< [31:27] Reserved
    } B;
} hw_ddr_cr09_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR09 register
 */
//@{
#define HW_DDR_CR09_ADDR         (REGS_DDR_BASE + 0x24U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR09              (*(__IO hw_ddr_cr09_t *) HW_DDR_CR09_ADDR)
#define HW_DDR_CR09_RD()         (HW_DDR_CR09.U)
#define HW_DDR_CR09_WR(v)        (HW_DDR_CR09.U = (v))
#define HW_DDR_CR09_SET(v)       (HW_DDR_CR09_WR(HW_DDR_CR09_RD() |  (v)))
#define HW_DDR_CR09_CLR(v)       (HW_DDR_CR09_WR(HW_DDR_CR09_RD() & ~(v)))
#define HW_DDR_CR09_TOG(v)       (HW_DDR_CR09_WR(HW_DDR_CR09_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR09 bitfields
 */

/*!
 * @name Register DDR_CR09, field TDLL[15:0] (RW)
 *
 * DLL lock time in cycles.
 */
//@{
#define BP_DDR_CR09_TDLL     (0U)          //!< Bit position for DDR_CR09_TDLL.
#define BM_DDR_CR09_TDLL     (0x0000FFFFU) //!< Bit mask for DDR_CR09_TDLL.
#define BS_DDR_CR09_TDLL     (16U)         //!< Bit field size in bits for DDR_CR09_TDLL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR09_TDLL field.
#define BR_DDR_CR09_TDLL     (HW_DDR_CR09.B.TDLL)
#endif

//! @brief Format value for bitfield DDR_CR09_TDLL.
#define BF_DDR_CR09_TDLL(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR09_TDLL), uint32_t) & BM_DDR_CR09_TDLL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TDLL field to a new value.
#define BW_DDR_CR09_TDLL(v)  (HW_DDR_CR09_WR((HW_DDR_CR09_RD() & ~BM_DDR_CR09_TDLL) | BF_DDR_CR09_TDLL(v)))
#endif
//@}

/*!
 * @name Register DDR_CR09, field NOCMD[16] (RW)
 *
 * Disable DRAM commands until DLL initialization is complete and TDLL expires.
 *
 * Values:
 * - 0 - Issue only REF and PRE commands during DLL initialization of the DRAM
 *     devices. If PRE commands are issued before DLL initialization is complete,
 *     the command is executed immediately and the DLL initialization continues.
 * - 1 - Do not issue any type of command during DLL initialization of the DRAM
 *     devices. If any other commands are issued, they are held until DLL
 *     initialization completes.
 */
//@{
#define BP_DDR_CR09_NOCMD    (16U)         //!< Bit position for DDR_CR09_NOCMD.
#define BM_DDR_CR09_NOCMD    (0x00010000U) //!< Bit mask for DDR_CR09_NOCMD.
#define BS_DDR_CR09_NOCMD    (1U)          //!< Bit field size in bits for DDR_CR09_NOCMD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR09_NOCMD field.
#define BR_DDR_CR09_NOCMD    (BITBAND_ACCESS32(HW_DDR_CR09_ADDR, BP_DDR_CR09_NOCMD))
#endif

//! @brief Format value for bitfield DDR_CR09_NOCMD.
#define BF_DDR_CR09_NOCMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR09_NOCMD), uint32_t) & BM_DDR_CR09_NOCMD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the NOCMD field to a new value.
#define BW_DDR_CR09_NOCMD(v) (BITBAND_ACCESS32(HW_DDR_CR09_ADDR, BP_DDR_CR09_NOCMD) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR09, field BSTLEN[26:24] (RW)
 *
 * Defines the memory burst length encoding that will be programmed into the
 * DRAM devices at initialization. The mode is programmed in the dram_class
 * parameter.
 *
 * Values:
 * - 000 - Reserved.
 * - 001 - Two memory words - only applicable if the reduc parameter is set to
 *     'b0 for operation in full datapath mode. Applicable for these memory
 *     systems: DDR1 (dram_class = 'b0000) LPDDR1 (dram_class = 'b0001).
 * - 010 - Four memory words. Applicable for these memory systems: DDR1
 *     (dram_class = 'b0000) LPDDR1 (dram_class = 'b0001) DDR2 (dram_class = 'b0100).
 * - 011 - Eight memory words. Applicable for these memory systems: DDR1
 *     (dram_class = 'b0000) LPDDR1 (dram_class = 'b0001).
 * - 100 - Reserved
 * - 111 - Reserved.
 */
//@{
#define BP_DDR_CR09_BSTLEN   (24U)         //!< Bit position for DDR_CR09_BSTLEN.
#define BM_DDR_CR09_BSTLEN   (0x07000000U) //!< Bit mask for DDR_CR09_BSTLEN.
#define BS_DDR_CR09_BSTLEN   (3U)          //!< Bit field size in bits for DDR_CR09_BSTLEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR09_BSTLEN field.
#define BR_DDR_CR09_BSTLEN   (HW_DDR_CR09.B.BSTLEN)
#endif

//! @brief Format value for bitfield DDR_CR09_BSTLEN.
#define BF_DDR_CR09_BSTLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR09_BSTLEN), uint32_t) & BM_DDR_CR09_BSTLEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BSTLEN field to a new value.
#define BW_DDR_CR09_BSTLEN(v) (HW_DDR_CR09_WR((HW_DDR_CR09_RD() & ~BM_DDR_CR09_BSTLEN) | BF_DDR_CR09_BSTLEN(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR10 - DDR Control Register 10
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR10 - DDR Control Register 10 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr10
{
    uint32_t U;
    struct _hw_ddr_cr10_bitfields
    {
        uint32_t TFAW : 6;             //!< [5:0] Time FAW
        uint32_t RESERVED0 : 2;        //!< [7:6] Reserved
        uint32_t TCPD : 16;            //!< [23:8] Time Clock Enable to Precharge Delay
        uint32_t TRPAB : 4;            //!< [27:24] TRP All Bank
        uint32_t RESERVED1 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr10_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR10 register
 */
//@{
#define HW_DDR_CR10_ADDR         (REGS_DDR_BASE + 0x28U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR10              (*(__IO hw_ddr_cr10_t *) HW_DDR_CR10_ADDR)
#define HW_DDR_CR10_RD()         (HW_DDR_CR10.U)
#define HW_DDR_CR10_WR(v)        (HW_DDR_CR10.U = (v))
#define HW_DDR_CR10_SET(v)       (HW_DDR_CR10_WR(HW_DDR_CR10_RD() |  (v)))
#define HW_DDR_CR10_CLR(v)       (HW_DDR_CR10_WR(HW_DDR_CR10_RD() & ~(v)))
#define HW_DDR_CR10_TOG(v)       (HW_DDR_CR10_WR(HW_DDR_CR10_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR10 bitfields
 */

/*!
 * @name Register DDR_CR10, field TFAW[5:0] (RW)
 *
 * Defines the DRAM t FAW parameter in cycles.
 */
//@{
#define BP_DDR_CR10_TFAW     (0U)          //!< Bit position for DDR_CR10_TFAW.
#define BM_DDR_CR10_TFAW     (0x0000003FU) //!< Bit mask for DDR_CR10_TFAW.
#define BS_DDR_CR10_TFAW     (6U)          //!< Bit field size in bits for DDR_CR10_TFAW.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR10_TFAW field.
#define BR_DDR_CR10_TFAW     (HW_DDR_CR10.B.TFAW)
#endif

//! @brief Format value for bitfield DDR_CR10_TFAW.
#define BF_DDR_CR10_TFAW(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR10_TFAW), uint32_t) & BM_DDR_CR10_TFAW)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TFAW field to a new value.
#define BW_DDR_CR10_TFAW(v)  (HW_DDR_CR10_WR((HW_DDR_CR10_RD() & ~BM_DDR_CR10_TFAW) | BF_DDR_CR10_TFAW(v)))
#endif
//@}

/*!
 * @name Register DDR_CR10, field TCPD[23:8] (RW)
 *
 * Defines the DRAM TCPD (clock enable to precharge delay time) parameter in
 * cycles.
 */
//@{
#define BP_DDR_CR10_TCPD     (8U)          //!< Bit position for DDR_CR10_TCPD.
#define BM_DDR_CR10_TCPD     (0x00FFFF00U) //!< Bit mask for DDR_CR10_TCPD.
#define BS_DDR_CR10_TCPD     (16U)         //!< Bit field size in bits for DDR_CR10_TCPD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR10_TCPD field.
#define BR_DDR_CR10_TCPD     (HW_DDR_CR10.B.TCPD)
#endif

//! @brief Format value for bitfield DDR_CR10_TCPD.
#define BF_DDR_CR10_TCPD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR10_TCPD), uint32_t) & BM_DDR_CR10_TCPD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TCPD field to a new value.
#define BW_DDR_CR10_TCPD(v)  (HW_DDR_CR10_WR((HW_DDR_CR10_RD() & ~BM_DDR_CR10_TCPD) | BF_DDR_CR10_TCPD(v)))
#endif
//@}

/*!
 * @name Register DDR_CR10, field TRPAB[27:24] (RW)
 *
 * DRAM TRP All Bank parameter in cycles.
 */
//@{
#define BP_DDR_CR10_TRPAB    (24U)         //!< Bit position for DDR_CR10_TRPAB.
#define BM_DDR_CR10_TRPAB    (0x0F000000U) //!< Bit mask for DDR_CR10_TRPAB.
#define BS_DDR_CR10_TRPAB    (4U)          //!< Bit field size in bits for DDR_CR10_TRPAB.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR10_TRPAB field.
#define BR_DDR_CR10_TRPAB    (HW_DDR_CR10.B.TRPAB)
#endif

//! @brief Format value for bitfield DDR_CR10_TRPAB.
#define BF_DDR_CR10_TRPAB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR10_TRPAB), uint32_t) & BM_DDR_CR10_TRPAB)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRPAB field to a new value.
#define BW_DDR_CR10_TRPAB(v) (HW_DDR_CR10_WR((HW_DDR_CR10_RD() & ~BM_DDR_CR10_TRPAB) | BF_DDR_CR10_TRPAB(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR11 - DDR Control Register 11
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR11 - DDR Control Register 11 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr11
{
    uint32_t U;
    struct _hw_ddr_cr11_bitfields
    {
        uint32_t REGDIMM : 1;          //!< [0] Registered DIMM
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t AREF : 1;             //!< [8] Auto Refresh
        uint32_t RESERVED1 : 7;        //!< [15:9] Reserved
        uint32_t AREFMODE : 1;         //!< [16] Auto Refresh Mode
        uint32_t RESERVED2 : 7;        //!< [23:17] Reserved
        uint32_t TREFEN : 1;           //!< [24]
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr11_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR11 register
 */
//@{
#define HW_DDR_CR11_ADDR         (REGS_DDR_BASE + 0x2CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR11              (*(__IO hw_ddr_cr11_t *) HW_DDR_CR11_ADDR)
#define HW_DDR_CR11_RD()         (HW_DDR_CR11.U)
#define HW_DDR_CR11_WR(v)        (HW_DDR_CR11.U = (v))
#define HW_DDR_CR11_SET(v)       (HW_DDR_CR11_WR(HW_DDR_CR11_RD() |  (v)))
#define HW_DDR_CR11_CLR(v)       (HW_DDR_CR11_WR(HW_DDR_CR11_RD() & ~(v)))
#define HW_DDR_CR11_TOG(v)       (HW_DDR_CR11_WR(HW_DDR_CR11_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR11 bitfields
 */

/*!
 * @name Register DDR_CR11, field REGDIMM[0] (RW)
 *
 * Enables registered DIMM operations to control the address and command
 * pipeline of the memory controller. 0 Normal operation 1 Enable registered DIMM
 * operation
 */
//@{
#define BP_DDR_CR11_REGDIMM  (0U)          //!< Bit position for DDR_CR11_REGDIMM.
#define BM_DDR_CR11_REGDIMM  (0x00000001U) //!< Bit mask for DDR_CR11_REGDIMM.
#define BS_DDR_CR11_REGDIMM  (1U)          //!< Bit field size in bits for DDR_CR11_REGDIMM.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR11_REGDIMM field.
#define BR_DDR_CR11_REGDIMM  (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_REGDIMM))
#endif

//! @brief Format value for bitfield DDR_CR11_REGDIMM.
#define BF_DDR_CR11_REGDIMM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR11_REGDIMM), uint32_t) & BM_DDR_CR11_REGDIMM)

#ifndef __LANGUAGE_ASM__
//! @brief Set the REGDIMM field to a new value.
#define BW_DDR_CR11_REGDIMM(v) (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_REGDIMM) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR11, field AREF[8] (WO)
 *
 * Trigger auto-refresh at boundary specified by AUTO_REFRESH_MODE. This bit
 * always reads zero. If there are any open banks when this parameter is set, the
 * memory controller automatically closes these banks before issuing the
 * auto-refresh command. 0 No action 1 Issue auto-refresh to the DRAM devices
 */
//@{
#define BP_DDR_CR11_AREF     (8U)          //!< Bit position for DDR_CR11_AREF.
#define BM_DDR_CR11_AREF     (0x00000100U) //!< Bit mask for DDR_CR11_AREF.
#define BS_DDR_CR11_AREF     (1U)          //!< Bit field size in bits for DDR_CR11_AREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR11_AREF field.
#define BR_DDR_CR11_AREF     (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_AREF))
#endif

//! @brief Format value for bitfield DDR_CR11_AREF.
#define BF_DDR_CR11_AREF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR11_AREF), uint32_t) & BM_DDR_CR11_AREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AREF field to a new value.
#define BW_DDR_CR11_AREF(v)  (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_AREF) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR11, field AREFMODE[16] (RW)
 *
 * Define auto refresh to occur at the next burst or command boundary. 0 Issue
 * refresh on the next DRAM burst boundary, even if the current command is not
 * complete 1 Issue refresh on the next command boundary. If a refresh is required
 * to memory, the controller delays this refresh until the end of the current
 * transaction (if the transaction is fully contained inside a single page), or until
 * the current transaction hits the end of the current page.
 */
//@{
#define BP_DDR_CR11_AREFMODE (16U)         //!< Bit position for DDR_CR11_AREFMODE.
#define BM_DDR_CR11_AREFMODE (0x00010000U) //!< Bit mask for DDR_CR11_AREFMODE.
#define BS_DDR_CR11_AREFMODE (1U)          //!< Bit field size in bits for DDR_CR11_AREFMODE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR11_AREFMODE field.
#define BR_DDR_CR11_AREFMODE (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_AREFMODE))
#endif

//! @brief Format value for bitfield DDR_CR11_AREFMODE.
#define BF_DDR_CR11_AREFMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR11_AREFMODE), uint32_t) & BM_DDR_CR11_AREFMODE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AREFMODE field to a new value.
#define BW_DDR_CR11_AREFMODE(v) (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_AREFMODE) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR11, field TREFEN[24] (RW)
 *
 * Enables refresh commands. If command refresh mode is configured, then refresh
 * commands are automatically issued based on the internal CR31[TREF] counter
 * and any refresh commands sent through the command interface or the register
 * interface. 0 Refresh commands disabled 1 Refresh commands enabled
 */
//@{
#define BP_DDR_CR11_TREFEN   (24U)         //!< Bit position for DDR_CR11_TREFEN.
#define BM_DDR_CR11_TREFEN   (0x01000000U) //!< Bit mask for DDR_CR11_TREFEN.
#define BS_DDR_CR11_TREFEN   (1U)          //!< Bit field size in bits for DDR_CR11_TREFEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR11_TREFEN field.
#define BR_DDR_CR11_TREFEN   (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_TREFEN))
#endif

//! @brief Format value for bitfield DDR_CR11_TREFEN.
#define BF_DDR_CR11_TREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR11_TREFEN), uint32_t) & BM_DDR_CR11_TREFEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TREFEN field to a new value.
#define BW_DDR_CR11_TREFEN(v) (BITBAND_ACCESS32(HW_DDR_CR11_ADDR, BP_DDR_CR11_TREFEN) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR12 - DDR Control Register 12
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR12 - DDR Control Register 12 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr12
{
    uint32_t U;
    struct _hw_ddr_cr12_bitfields
    {
        uint32_t TRFC : 10;            //!< [9:0] Time Refresh Command
        uint32_t RESERVED0 : 6;        //!< [15:10] Reserved
        uint32_t TREF : 14;            //!< [29:16] Time Refresh
        uint32_t RESERVED1 : 2;        //!< [31:30] Reserved
    } B;
} hw_ddr_cr12_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR12 register
 */
//@{
#define HW_DDR_CR12_ADDR         (REGS_DDR_BASE + 0x30U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR12              (*(__IO hw_ddr_cr12_t *) HW_DDR_CR12_ADDR)
#define HW_DDR_CR12_RD()         (HW_DDR_CR12.U)
#define HW_DDR_CR12_WR(v)        (HW_DDR_CR12.U = (v))
#define HW_DDR_CR12_SET(v)       (HW_DDR_CR12_WR(HW_DDR_CR12_RD() |  (v)))
#define HW_DDR_CR12_CLR(v)       (HW_DDR_CR12_WR(HW_DDR_CR12_RD() & ~(v)))
#define HW_DDR_CR12_TOG(v)       (HW_DDR_CR12_WR(HW_DDR_CR12_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR12 bitfields
 */

/*!
 * @name Register DDR_CR12, field TRFC[9:0] (RW)
 *
 * Defines the DRAM refresh command time (TRFC) in cycles.
 */
//@{
#define BP_DDR_CR12_TRFC     (0U)          //!< Bit position for DDR_CR12_TRFC.
#define BM_DDR_CR12_TRFC     (0x000003FFU) //!< Bit mask for DDR_CR12_TRFC.
#define BS_DDR_CR12_TRFC     (10U)         //!< Bit field size in bits for DDR_CR12_TRFC.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR12_TRFC field.
#define BR_DDR_CR12_TRFC     (HW_DDR_CR12.B.TRFC)
#endif

//! @brief Format value for bitfield DDR_CR12_TRFC.
#define BF_DDR_CR12_TRFC(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR12_TRFC), uint32_t) & BM_DDR_CR12_TRFC)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TRFC field to a new value.
#define BW_DDR_CR12_TRFC(v)  (HW_DDR_CR12_WR((HW_DDR_CR12_RD() & ~BM_DDR_CR12_TRFC) | BF_DDR_CR12_TRFC(v)))
#endif
//@}

/*!
 * @name Register DDR_CR12, field TREF[29:16] (RW)
 *
 * Defines the DRAM cycles between refresh commands (TREF) in cycles.
 */
//@{
#define BP_DDR_CR12_TREF     (16U)         //!< Bit position for DDR_CR12_TREF.
#define BM_DDR_CR12_TREF     (0x3FFF0000U) //!< Bit mask for DDR_CR12_TREF.
#define BS_DDR_CR12_TREF     (14U)         //!< Bit field size in bits for DDR_CR12_TREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR12_TREF field.
#define BR_DDR_CR12_TREF     (HW_DDR_CR12.B.TREF)
#endif

//! @brief Format value for bitfield DDR_CR12_TREF.
#define BF_DDR_CR12_TREF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR12_TREF), uint32_t) & BM_DDR_CR12_TREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TREF field to a new value.
#define BW_DDR_CR12_TREF(v)  (HW_DDR_CR12_WR((HW_DDR_CR12_RD() & ~BM_DDR_CR12_TREF) | BF_DDR_CR12_TREF(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR13 - DDR Control Register 13
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR13 - DDR Control Register 13 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr13
{
    uint32_t U;
    struct _hw_ddr_cr13_bitfields
    {
        uint32_t TREFINT : 14;         //!< [13:0] Reserved
        uint32_t RESERVED0 : 2;        //!< [15:14] Reserved
        uint32_t PD : 1;               //!< [16] Power Down
        uint32_t RESERVED1 : 15;       //!< [31:17] Reserved
    } B;
} hw_ddr_cr13_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR13 register
 */
//@{
#define HW_DDR_CR13_ADDR         (REGS_DDR_BASE + 0x34U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR13              (*(__IO hw_ddr_cr13_t *) HW_DDR_CR13_ADDR)
#define HW_DDR_CR13_RD()         (HW_DDR_CR13.U)
#define HW_DDR_CR13_WR(v)        (HW_DDR_CR13.U = (v))
#define HW_DDR_CR13_SET(v)       (HW_DDR_CR13_WR(HW_DDR_CR13_RD() |  (v)))
#define HW_DDR_CR13_CLR(v)       (HW_DDR_CR13_WR(HW_DDR_CR13_RD() & ~(v)))
#define HW_DDR_CR13_TOG(v)       (HW_DDR_CR13_WR(HW_DDR_CR13_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR13 bitfields
 */

/*!
 * @name Register DDR_CR13, field TREFINT[13:0] (RW)
 */
//@{
#define BP_DDR_CR13_TREFINT  (0U)          //!< Bit position for DDR_CR13_TREFINT.
#define BM_DDR_CR13_TREFINT  (0x00003FFFU) //!< Bit mask for DDR_CR13_TREFINT.
#define BS_DDR_CR13_TREFINT  (14U)         //!< Bit field size in bits for DDR_CR13_TREFINT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR13_TREFINT field.
#define BR_DDR_CR13_TREFINT  (HW_DDR_CR13.B.TREFINT)
#endif

//! @brief Format value for bitfield DDR_CR13_TREFINT.
#define BF_DDR_CR13_TREFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR13_TREFINT), uint32_t) & BM_DDR_CR13_TREFINT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TREFINT field to a new value.
#define BW_DDR_CR13_TREFINT(v) (HW_DDR_CR13_WR((HW_DDR_CR13_RD() & ~BM_DDR_CR13_TREFINT) | BF_DDR_CR13_TREFINT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR13, field PD[16] (RW)
 *
 * Disable clock enable and set DRAMs into the power-down state.
 *
 * Values:
 * - 0 - Enable full power state
 * - 1 - The memory controller completes processing of the current burst for the
 *     current transaction (if any), issues a precharge all command, and
 *     disables the clock enable signal to the DRAM devices. Any subsequent commands in
 *     the command queue are suspended until this bit is cleared.
 */
//@{
#define BP_DDR_CR13_PD       (16U)         //!< Bit position for DDR_CR13_PD.
#define BM_DDR_CR13_PD       (0x00010000U) //!< Bit mask for DDR_CR13_PD.
#define BS_DDR_CR13_PD       (1U)          //!< Bit field size in bits for DDR_CR13_PD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR13_PD field.
#define BR_DDR_CR13_PD       (BITBAND_ACCESS32(HW_DDR_CR13_ADDR, BP_DDR_CR13_PD))
#endif

//! @brief Format value for bitfield DDR_CR13_PD.
#define BF_DDR_CR13_PD(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR13_PD), uint32_t) & BM_DDR_CR13_PD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PD field to a new value.
#define BW_DDR_CR13_PD(v)    (BITBAND_ACCESS32(HW_DDR_CR13_ADDR, BP_DDR_CR13_PD) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR14 - DDR Control Register 14
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR14 - DDR Control Register 14 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr14
{
    uint32_t U;
    struct _hw_ddr_cr14_bitfields
    {
        uint32_t TPDEX : 16;           //!< [15:0] Time Power Down Exit
        uint32_t TXSR : 16;            //!< [31:16] Time Exit Self Refresh
    } B;
} hw_ddr_cr14_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR14 register
 */
//@{
#define HW_DDR_CR14_ADDR         (REGS_DDR_BASE + 0x38U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR14              (*(__IO hw_ddr_cr14_t *) HW_DDR_CR14_ADDR)
#define HW_DDR_CR14_RD()         (HW_DDR_CR14.U)
#define HW_DDR_CR14_WR(v)        (HW_DDR_CR14.U = (v))
#define HW_DDR_CR14_SET(v)       (HW_DDR_CR14_WR(HW_DDR_CR14_RD() |  (v)))
#define HW_DDR_CR14_CLR(v)       (HW_DDR_CR14_WR(HW_DDR_CR14_RD() & ~(v)))
#define HW_DDR_CR14_TOG(v)       (HW_DDR_CR14_WR(HW_DDR_CR14_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR14 bitfields
 */

/*!
 * @name Register DDR_CR14, field TPDEX[15:0] (RW)
 *
 * Defines the DRAM power-down exit command period in cycles.
 */
//@{
#define BP_DDR_CR14_TPDEX    (0U)          //!< Bit position for DDR_CR14_TPDEX.
#define BM_DDR_CR14_TPDEX    (0x0000FFFFU) //!< Bit mask for DDR_CR14_TPDEX.
#define BS_DDR_CR14_TPDEX    (16U)         //!< Bit field size in bits for DDR_CR14_TPDEX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR14_TPDEX field.
#define BR_DDR_CR14_TPDEX    (HW_DDR_CR14.B.TPDEX)
#endif

//! @brief Format value for bitfield DDR_CR14_TPDEX.
#define BF_DDR_CR14_TPDEX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR14_TPDEX), uint32_t) & BM_DDR_CR14_TPDEX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TPDEX field to a new value.
#define BW_DDR_CR14_TPDEX(v) (HW_DDR_CR14_WR((HW_DDR_CR14_RD() & ~BM_DDR_CR14_TPDEX) | BF_DDR_CR14_TPDEX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR14, field TXSR[31:16] (RW)
 *
 * Defines the DRAM self-refresh exit time (TXSR) in cycles.
 */
//@{
#define BP_DDR_CR14_TXSR     (16U)         //!< Bit position for DDR_CR14_TXSR.
#define BM_DDR_CR14_TXSR     (0xFFFF0000U) //!< Bit mask for DDR_CR14_TXSR.
#define BS_DDR_CR14_TXSR     (16U)         //!< Bit field size in bits for DDR_CR14_TXSR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR14_TXSR field.
#define BR_DDR_CR14_TXSR     (HW_DDR_CR14.B.TXSR)
#endif

//! @brief Format value for bitfield DDR_CR14_TXSR.
#define BF_DDR_CR14_TXSR(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR14_TXSR), uint32_t) & BM_DDR_CR14_TXSR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TXSR field to a new value.
#define BW_DDR_CR14_TXSR(v)  (HW_DDR_CR14_WR((HW_DDR_CR14_RD() & ~BM_DDR_CR14_TXSR) | BF_DDR_CR14_TXSR(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR15 - DDR Control Register 15
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR15 - DDR Control Register 15 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr15
{
    uint32_t U;
    struct _hw_ddr_cr15_bitfields
    {
        uint32_t TXSNR : 16;           //!< [15:0] TXSNR parameter
        uint32_t SREF : 1;             //!< [16] Self Refresh
        uint32_t RESERVED0 : 7;        //!< [23:17] Reserved
        uint32_t PUREF : 1;            //!< [24] Power Up Refresh
        uint32_t RESERVED1 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr15_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR15 register
 */
//@{
#define HW_DDR_CR15_ADDR         (REGS_DDR_BASE + 0x3CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR15              (*(__IO hw_ddr_cr15_t *) HW_DDR_CR15_ADDR)
#define HW_DDR_CR15_RD()         (HW_DDR_CR15.U)
#define HW_DDR_CR15_WR(v)        (HW_DDR_CR15.U = (v))
#define HW_DDR_CR15_SET(v)       (HW_DDR_CR15_WR(HW_DDR_CR15_RD() |  (v)))
#define HW_DDR_CR15_CLR(v)       (HW_DDR_CR15_WR(HW_DDR_CR15_RD() & ~(v)))
#define HW_DDR_CR15_TOG(v)       (HW_DDR_CR15_WR(HW_DDR_CR15_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR15 bitfields
 */

/*!
 * @name Register DDR_CR15, field TXSNR[15:0] (RW)
 *
 * Defines the DRAM TXSNR parameter in cycles.
 */
//@{
#define BP_DDR_CR15_TXSNR    (0U)          //!< Bit position for DDR_CR15_TXSNR.
#define BM_DDR_CR15_TXSNR    (0x0000FFFFU) //!< Bit mask for DDR_CR15_TXSNR.
#define BS_DDR_CR15_TXSNR    (16U)         //!< Bit field size in bits for DDR_CR15_TXSNR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR15_TXSNR field.
#define BR_DDR_CR15_TXSNR    (HW_DDR_CR15.B.TXSNR)
#endif

//! @brief Format value for bitfield DDR_CR15_TXSNR.
#define BF_DDR_CR15_TXSNR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR15_TXSNR), uint32_t) & BM_DDR_CR15_TXSNR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the TXSNR field to a new value.
#define BW_DDR_CR15_TXSNR(v) (HW_DDR_CR15_WR((HW_DDR_CR15_RD() & ~BM_DDR_CR15_TXSNR) | BF_DDR_CR15_TXSNR(v)))
#endif
//@}

/*!
 * @name Register DDR_CR15, field SREF[16] (RW)
 *
 * Place DRAMs into self-refresh mode. 0 Disable self-refresh mode 1 Initiate
 * self-refresh mode of the DRAM devices. The burst of the current transaction (if
 * any) completes, all banks are closed, the self-refresh command is issued to
 * the DRAM, and the clock enable signal is negated. The system remains in
 * self-refresh mode until this bit is cleared. The DRAM devices return to normal
 * operating mode after the self-refresh exit time (TXSR) of the device . The memory
 * controller resumes processing of the commands from the interruption point.
 */
//@{
#define BP_DDR_CR15_SREF     (16U)         //!< Bit position for DDR_CR15_SREF.
#define BM_DDR_CR15_SREF     (0x00010000U) //!< Bit mask for DDR_CR15_SREF.
#define BS_DDR_CR15_SREF     (1U)          //!< Bit field size in bits for DDR_CR15_SREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR15_SREF field.
#define BR_DDR_CR15_SREF     (BITBAND_ACCESS32(HW_DDR_CR15_ADDR, BP_DDR_CR15_SREF))
#endif

//! @brief Format value for bitfield DDR_CR15_SREF.
#define BF_DDR_CR15_SREF(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR15_SREF), uint32_t) & BM_DDR_CR15_SREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SREF field to a new value.
#define BW_DDR_CR15_SREF(v)  (BITBAND_ACCESS32(HW_DDR_CR15_ADDR, BP_DDR_CR15_SREF) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR15, field PUREF[24] (RW)
 *
 * Allows controller to exit power-down mode by executing a self-refresh instead
 * of full memory initialization. This fields allows you to skip full
 * initialization when the DRAM devices are in a known self-refresh state. For this silicon
 * revision, clear this bit. This may result in a t XSNR violation. Consult your
 * memory vendor to understand the exact implications of this.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR15_PUREF    (24U)         //!< Bit position for DDR_CR15_PUREF.
#define BM_DDR_CR15_PUREF    (0x01000000U) //!< Bit mask for DDR_CR15_PUREF.
#define BS_DDR_CR15_PUREF    (1U)          //!< Bit field size in bits for DDR_CR15_PUREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR15_PUREF field.
#define BR_DDR_CR15_PUREF    (BITBAND_ACCESS32(HW_DDR_CR15_ADDR, BP_DDR_CR15_PUREF))
#endif

//! @brief Format value for bitfield DDR_CR15_PUREF.
#define BF_DDR_CR15_PUREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR15_PUREF), uint32_t) & BM_DDR_CR15_PUREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUREF field to a new value.
#define BW_DDR_CR15_PUREF(v) (BITBAND_ACCESS32(HW_DDR_CR15_ADDR, BP_DDR_CR15_PUREF) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR16 - DDR Control Register 16
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR16 - DDR Control Register 16 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr16
{
    uint32_t U;
    struct _hw_ddr_cr16_bitfields
    {
        uint32_t QKREF : 1;            //!< [0] Quick Refresh
        uint32_t RESERVED0 : 7;        //!< [7:1]
        uint32_t CLKDLY : 3;           //!< [10:8] Clock Delay
        uint32_t RESERVED1 : 5;        //!< [15:11] Reserved
        uint32_t LPCTRL : 5;           //!< [20:16] Low Power Control
        uint32_t RESERVED2 : 11;       //!< [31:21] Reserved
    } B;
} hw_ddr_cr16_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR16 register
 */
//@{
#define HW_DDR_CR16_ADDR         (REGS_DDR_BASE + 0x40U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR16              (*(__IO hw_ddr_cr16_t *) HW_DDR_CR16_ADDR)
#define HW_DDR_CR16_RD()         (HW_DDR_CR16.U)
#define HW_DDR_CR16_WR(v)        (HW_DDR_CR16.U = (v))
#define HW_DDR_CR16_SET(v)       (HW_DDR_CR16_WR(HW_DDR_CR16_RD() |  (v)))
#define HW_DDR_CR16_CLR(v)       (HW_DDR_CR16_WR(HW_DDR_CR16_RD() & ~(v)))
#define HW_DDR_CR16_TOG(v)       (HW_DDR_CR16_WR(HW_DDR_CR16_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR16 bitfields
 */

/*!
 * @name Register DDR_CR16, field QKREF[0] (RW)
 *
 * Enable quick self-refresh. Allows user to interrupt memory initialization to
 * enter self-refresh mode when a power loss is detected during the
 * initialization process.
 *
 * Values:
 * - 0 - Continue memory initialization
 * - 1 - Interrupt memory initialization and enter self-refresh mode
 */
//@{
#define BP_DDR_CR16_QKREF    (0U)          //!< Bit position for DDR_CR16_QKREF.
#define BM_DDR_CR16_QKREF    (0x00000001U) //!< Bit mask for DDR_CR16_QKREF.
#define BS_DDR_CR16_QKREF    (1U)          //!< Bit field size in bits for DDR_CR16_QKREF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR16_QKREF field.
#define BR_DDR_CR16_QKREF    (BITBAND_ACCESS32(HW_DDR_CR16_ADDR, BP_DDR_CR16_QKREF))
#endif

//! @brief Format value for bitfield DDR_CR16_QKREF.
#define BF_DDR_CR16_QKREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR16_QKREF), uint32_t) & BM_DDR_CR16_QKREF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the QKREF field to a new value.
#define BW_DDR_CR16_QKREF(v) (BITBAND_ACCESS32(HW_DDR_CR16_ADDR, BP_DDR_CR16_QKREF) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR16, field CLKDLY[10:8] (RW)
 *
 * Additional cycles to delay CLK for status reporting.
 */
//@{
#define BP_DDR_CR16_CLKDLY   (8U)          //!< Bit position for DDR_CR16_CLKDLY.
#define BM_DDR_CR16_CLKDLY   (0x00000700U) //!< Bit mask for DDR_CR16_CLKDLY.
#define BS_DDR_CR16_CLKDLY   (3U)          //!< Bit field size in bits for DDR_CR16_CLKDLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR16_CLKDLY field.
#define BR_DDR_CR16_CLKDLY   (HW_DDR_CR16.B.CLKDLY)
#endif

//! @brief Format value for bitfield DDR_CR16_CLKDLY.
#define BF_DDR_CR16_CLKDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR16_CLKDLY), uint32_t) & BM_DDR_CR16_CLKDLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKDLY field to a new value.
#define BW_DDR_CR16_CLKDLY(v) (HW_DDR_CR16_WR((HW_DDR_CR16_RD() & ~BM_DDR_CR16_CLKDLY) | BF_DDR_CR16_CLKDLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR16, field LPCTRL[20:16] (RW)
 *
 * Controls entry into the low power modes. Bit[20]: Memory power-down mode
 * (mode 1) Bit[19]: Memory power-down with memory clock gating mode (mode 2)
 * Bit[18]: Memory self-refresh mode (mode 3) Bit[17]: Memory self-refresh with memory
 * clock gating mode (mode 4) Bit[16]: Memory self-refresh with memory and
 * controller clock gating mode (mode 5)
 *
 * Values:
 * - 0 - Disable
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR16_LPCTRL   (16U)         //!< Bit position for DDR_CR16_LPCTRL.
#define BM_DDR_CR16_LPCTRL   (0x001F0000U) //!< Bit mask for DDR_CR16_LPCTRL.
#define BS_DDR_CR16_LPCTRL   (5U)          //!< Bit field size in bits for DDR_CR16_LPCTRL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR16_LPCTRL field.
#define BR_DDR_CR16_LPCTRL   (HW_DDR_CR16.B.LPCTRL)
#endif

//! @brief Format value for bitfield DDR_CR16_LPCTRL.
#define BF_DDR_CR16_LPCTRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR16_LPCTRL), uint32_t) & BM_DDR_CR16_LPCTRL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPCTRL field to a new value.
#define BW_DDR_CR16_LPCTRL(v) (HW_DDR_CR16_WR((HW_DDR_CR16_RD() & ~BM_DDR_CR16_LPCTRL) | BF_DDR_CR16_LPCTRL(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR17 - DDR Control Register 17
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR17 - DDR Control Register 17 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr17
{
    uint32_t U;
    struct _hw_ddr_cr17_bitfields
    {
        uint32_t LPPDCNT : 16;         //!< [15:0] Low Power Power Down Count
        uint32_t LPRFCNT : 16;         //!< [31:16] Low Power Refresh Count
    } B;
} hw_ddr_cr17_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR17 register
 */
//@{
#define HW_DDR_CR17_ADDR         (REGS_DDR_BASE + 0x44U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR17              (*(__IO hw_ddr_cr17_t *) HW_DDR_CR17_ADDR)
#define HW_DDR_CR17_RD()         (HW_DDR_CR17.U)
#define HW_DDR_CR17_WR(v)        (HW_DDR_CR17.U = (v))
#define HW_DDR_CR17_SET(v)       (HW_DDR_CR17_WR(HW_DDR_CR17_RD() |  (v)))
#define HW_DDR_CR17_CLR(v)       (HW_DDR_CR17_WR(HW_DDR_CR17_RD() & ~(v)))
#define HW_DDR_CR17_TOG(v)       (HW_DDR_CR17_WR(HW_DDR_CR17_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR17 bitfields
 */

/*!
 * @name Register DDR_CR17, field LPPDCNT[15:0] (RW)
 *
 * Counts the number of idle cycles before memory power-down or power-down in
 * memory clock gating low power modes.
 */
//@{
#define BP_DDR_CR17_LPPDCNT  (0U)          //!< Bit position for DDR_CR17_LPPDCNT.
#define BM_DDR_CR17_LPPDCNT  (0x0000FFFFU) //!< Bit mask for DDR_CR17_LPPDCNT.
#define BS_DDR_CR17_LPPDCNT  (16U)         //!< Bit field size in bits for DDR_CR17_LPPDCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR17_LPPDCNT field.
#define BR_DDR_CR17_LPPDCNT  (HW_DDR_CR17.B.LPPDCNT)
#endif

//! @brief Format value for bitfield DDR_CR17_LPPDCNT.
#define BF_DDR_CR17_LPPDCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR17_LPPDCNT), uint32_t) & BM_DDR_CR17_LPPDCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPPDCNT field to a new value.
#define BW_DDR_CR17_LPPDCNT(v) (HW_DDR_CR17_WR((HW_DDR_CR17_RD() & ~BM_DDR_CR17_LPPDCNT) | BF_DDR_CR17_LPPDCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR17, field LPRFCNT[31:16] (RW)
 *
 * Counts the number of idle cycles to the next memory self-refresh low power
 * mode.
 */
//@{
#define BP_DDR_CR17_LPRFCNT  (16U)         //!< Bit position for DDR_CR17_LPRFCNT.
#define BM_DDR_CR17_LPRFCNT  (0xFFFF0000U) //!< Bit mask for DDR_CR17_LPRFCNT.
#define BS_DDR_CR17_LPRFCNT  (16U)         //!< Bit field size in bits for DDR_CR17_LPRFCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR17_LPRFCNT field.
#define BR_DDR_CR17_LPRFCNT  (HW_DDR_CR17.B.LPRFCNT)
#endif

//! @brief Format value for bitfield DDR_CR17_LPRFCNT.
#define BF_DDR_CR17_LPRFCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR17_LPRFCNT), uint32_t) & BM_DDR_CR17_LPRFCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPRFCNT field to a new value.
#define BW_DDR_CR17_LPRFCNT(v) (HW_DDR_CR17_WR((HW_DDR_CR17_RD() & ~BM_DDR_CR17_LPRFCNT) | BF_DDR_CR17_LPRFCNT(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR18 - DDR Control Register 18
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR18 - DDR Control Register 18 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr18
{
    uint32_t U;
    struct _hw_ddr_cr18_bitfields
    {
        uint32_t LPEXTCNT : 16;        //!< [15:0] Low Power External Count
        uint32_t LPAUTO : 5;           //!< [20:16] Low Power Auto
        uint32_t RESERVED0 : 11;       //!< [31:21] Reserved
    } B;
} hw_ddr_cr18_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR18 register
 */
//@{
#define HW_DDR_CR18_ADDR         (REGS_DDR_BASE + 0x48U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR18              (*(__IO hw_ddr_cr18_t *) HW_DDR_CR18_ADDR)
#define HW_DDR_CR18_RD()         (HW_DDR_CR18.U)
#define HW_DDR_CR18_WR(v)        (HW_DDR_CR18.U = (v))
#define HW_DDR_CR18_SET(v)       (HW_DDR_CR18_WR(HW_DDR_CR18_RD() |  (v)))
#define HW_DDR_CR18_CLR(v)       (HW_DDR_CR18_WR(HW_DDR_CR18_RD() & ~(v)))
#define HW_DDR_CR18_TOG(v)       (HW_DDR_CR18_WR(HW_DDR_CR18_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR18 bitfields
 */

/*!
 * @name Register DDR_CR18, field LPEXTCNT[15:0] (RW)
 *
 * Counts the number of idle cycles before memory self-refresh in memory clock
 * gating low power mode.
 */
//@{
#define BP_DDR_CR18_LPEXTCNT (0U)          //!< Bit position for DDR_CR18_LPEXTCNT.
#define BM_DDR_CR18_LPEXTCNT (0x0000FFFFU) //!< Bit mask for DDR_CR18_LPEXTCNT.
#define BS_DDR_CR18_LPEXTCNT (16U)         //!< Bit field size in bits for DDR_CR18_LPEXTCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR18_LPEXTCNT field.
#define BR_DDR_CR18_LPEXTCNT (HW_DDR_CR18.B.LPEXTCNT)
#endif

//! @brief Format value for bitfield DDR_CR18_LPEXTCNT.
#define BF_DDR_CR18_LPEXTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR18_LPEXTCNT), uint32_t) & BM_DDR_CR18_LPEXTCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPEXTCNT field to a new value.
#define BW_DDR_CR18_LPEXTCNT(v) (HW_DDR_CR18_WR((HW_DDR_CR18_RD() & ~BM_DDR_CR18_LPEXTCNT) | BF_DDR_CR18_LPEXTCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR18, field LPAUTO[20:16] (RW)
 *
 * Enables automatic entry into the low power mode on idle. Bit[20]: Memory
 * power-down mode (mode 1) Bit[19]: Memory power-down with memory clock gating mode
 * (mode 2) Bit[18]: Memory self-refresh mode (mode 3) Bit[17]: Memory
 * self-refresh with memory clock gating mode (mode 4) Bit[16]: Memory self-refresh with
 * memory and controller clock gating mode (mode 5) 0 Automatic entry into this
 * mode is disabled. You may enter the modes manually by setting the associated
 * LPCTRL bit. 1 The controller/memory automatically enters this mode when the proper
 * counters expire, and only if the associated LPCTRL is set.
 */
//@{
#define BP_DDR_CR18_LPAUTO   (16U)         //!< Bit position for DDR_CR18_LPAUTO.
#define BM_DDR_CR18_LPAUTO   (0x001F0000U) //!< Bit mask for DDR_CR18_LPAUTO.
#define BS_DDR_CR18_LPAUTO   (5U)          //!< Bit field size in bits for DDR_CR18_LPAUTO.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR18_LPAUTO field.
#define BR_DDR_CR18_LPAUTO   (HW_DDR_CR18.B.LPAUTO)
#endif

//! @brief Format value for bitfield DDR_CR18_LPAUTO.
#define BF_DDR_CR18_LPAUTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR18_LPAUTO), uint32_t) & BM_DDR_CR18_LPAUTO)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPAUTO field to a new value.
#define BW_DDR_CR18_LPAUTO(v) (HW_DDR_CR18_WR((HW_DDR_CR18_RD() & ~BM_DDR_CR18_LPAUTO) | BF_DDR_CR18_LPAUTO(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR19 - DDR Control Register 19
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR19 - DDR Control Register 19 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr19
{
    uint32_t U;
    struct _hw_ddr_cr19_bitfields
    {
        uint32_t LPINTCNT : 16;        //!< [15:0] Low Power Interval Count
        uint32_t LPRFHOLD : 16;        //!< [31:16] Low Power Refresh Hold
    } B;
} hw_ddr_cr19_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR19 register
 */
//@{
#define HW_DDR_CR19_ADDR         (REGS_DDR_BASE + 0x4CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR19              (*(__IO hw_ddr_cr19_t *) HW_DDR_CR19_ADDR)
#define HW_DDR_CR19_RD()         (HW_DDR_CR19.U)
#define HW_DDR_CR19_WR(v)        (HW_DDR_CR19.U = (v))
#define HW_DDR_CR19_SET(v)       (HW_DDR_CR19_WR(HW_DDR_CR19_RD() |  (v)))
#define HW_DDR_CR19_CLR(v)       (HW_DDR_CR19_WR(HW_DDR_CR19_RD() & ~(v)))
#define HW_DDR_CR19_TOG(v)       (HW_DDR_CR19_WR(HW_DDR_CR19_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR19 bitfields
 */

/*!
 * @name Register DDR_CR19, field LPINTCNT[15:0] (RW)
 *
 * Counts the number of idle cycles before memory self-refresh in memory and
 * controller clock gating low power mode. This parameter must be programmed to a
 * non-zero value for proper operation.
 */
//@{
#define BP_DDR_CR19_LPINTCNT (0U)          //!< Bit position for DDR_CR19_LPINTCNT.
#define BM_DDR_CR19_LPINTCNT (0x0000FFFFU) //!< Bit mask for DDR_CR19_LPINTCNT.
#define BS_DDR_CR19_LPINTCNT (16U)         //!< Bit field size in bits for DDR_CR19_LPINTCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR19_LPINTCNT field.
#define BR_DDR_CR19_LPINTCNT (HW_DDR_CR19.B.LPINTCNT)
#endif

//! @brief Format value for bitfield DDR_CR19_LPINTCNT.
#define BF_DDR_CR19_LPINTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR19_LPINTCNT), uint32_t) & BM_DDR_CR19_LPINTCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPINTCNT field to a new value.
#define BW_DDR_CR19_LPINTCNT(v) (HW_DDR_CR19_WR((HW_DDR_CR19_RD() & ~BM_DDR_CR19_LPINTCNT) | BF_DDR_CR19_LPINTCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR19, field LPRFHOLD[31:16] (RW)
 *
 * Re-sync counter for DLL in clock gate mode. Sets the number of cycles that
 * the memory controller waits before attempting to re-lock the DLL when using the
 * controller clock gating mode low power mode. This counter is only used in this
 * mode, the deepest low power mode. When this counter expires, the DLL is
 * ungated for at least 16 cycles during which the DLL attempts to re-lock. After 16
 * cycles elapse and the DLL locks, the DLL controller clock is gated again and
 * the counter resets to this value. If the DLL requires more than 16 cycles to
 * re-lock, then the ungated time is longer.
 */
//@{
#define BP_DDR_CR19_LPRFHOLD (16U)         //!< Bit position for DDR_CR19_LPRFHOLD.
#define BM_DDR_CR19_LPRFHOLD (0xFFFF0000U) //!< Bit mask for DDR_CR19_LPRFHOLD.
#define BS_DDR_CR19_LPRFHOLD (16U)         //!< Bit field size in bits for DDR_CR19_LPRFHOLD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR19_LPRFHOLD field.
#define BR_DDR_CR19_LPRFHOLD (HW_DDR_CR19.B.LPRFHOLD)
#endif

//! @brief Format value for bitfield DDR_CR19_LPRFHOLD.
#define BF_DDR_CR19_LPRFHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR19_LPRFHOLD), uint32_t) & BM_DDR_CR19_LPRFHOLD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPRFHOLD field to a new value.
#define BW_DDR_CR19_LPRFHOLD(v) (HW_DDR_CR19_WR((HW_DDR_CR19_RD() & ~BM_DDR_CR19_LPRFHOLD) | BF_DDR_CR19_LPRFHOLD(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR20 - DDR Control Register 20
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR20 - DDR Control Register 20 (RW)
 *
 * Reset value: 0x0C000000U
 */
typedef union _hw_ddr_cr20
{
    uint32_t U;
    struct _hw_ddr_cr20_bitfields
    {
        uint32_t LPRE : 2;             //!< [1:0] Low Power Refresh enable
        uint32_t RESERVED0 : 6;        //!< [7:2] Reserved
        uint32_t CKSRE : 4;            //!< [11:8]
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t CKSRX : 4;            //!< [19:16] Clock Self Refresh Exit
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t WRMD : 1;             //!< [24] Write Mode Register
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr20_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR20 register
 */
//@{
#define HW_DDR_CR20_ADDR         (REGS_DDR_BASE + 0x50U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR20              (*(__IO hw_ddr_cr20_t *) HW_DDR_CR20_ADDR)
#define HW_DDR_CR20_RD()         (HW_DDR_CR20.U)
#define HW_DDR_CR20_WR(v)        (HW_DDR_CR20.U = (v))
#define HW_DDR_CR20_SET(v)       (HW_DDR_CR20_WR(HW_DDR_CR20_RD() |  (v)))
#define HW_DDR_CR20_CLR(v)       (HW_DDR_CR20_WR(HW_DDR_CR20_RD() & ~(v)))
#define HW_DDR_CR20_TOG(v)       (HW_DDR_CR20_WR(HW_DDR_CR20_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR20 bitfields
 */

/*!
 * @name Register DDR_CR20, field LPRE[1:0] (RW)
 *
 * Sets whether refreshes will occur while the memory controller is in one of
 * the power-down modes. The refreshes will not occur while in any of the
 * self-refresh modes. This parameter is active low.
 *
 * Values:
 * - 00 - Refreshes occur
 * - 01 - Refreshes do not occur
 * - 10 - Reserved
 * - 11 - Reserved
 */
//@{
#define BP_DDR_CR20_LPRE     (0U)          //!< Bit position for DDR_CR20_LPRE.
#define BM_DDR_CR20_LPRE     (0x00000003U) //!< Bit mask for DDR_CR20_LPRE.
#define BS_DDR_CR20_LPRE     (2U)          //!< Bit field size in bits for DDR_CR20_LPRE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR20_LPRE field.
#define BR_DDR_CR20_LPRE     (HW_DDR_CR20.B.LPRE)
#endif

//! @brief Format value for bitfield DDR_CR20_LPRE.
#define BF_DDR_CR20_LPRE(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR20_LPRE), uint32_t) & BM_DDR_CR20_LPRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the LPRE field to a new value.
#define BW_DDR_CR20_LPRE(v)  (HW_DDR_CR20_WR((HW_DDR_CR20_RD() & ~BM_DDR_CR20_LPRE) | BF_DDR_CR20_LPRE(v)))
#endif
//@}

/*!
 * @name Register DDR_CR20, field CKSRE[11:8] (RW)
 *
 * Clock hold delay on self refresh entry. Sets the number of cycles to hold the
 * clock stable after entering self-refresh mode. The clock will run for a
 * minimum of cksre cycles after CLK falls.
 */
//@{
#define BP_DDR_CR20_CKSRE    (8U)          //!< Bit position for DDR_CR20_CKSRE.
#define BM_DDR_CR20_CKSRE    (0x00000F00U) //!< Bit mask for DDR_CR20_CKSRE.
#define BS_DDR_CR20_CKSRE    (4U)          //!< Bit field size in bits for DDR_CR20_CKSRE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR20_CKSRE field.
#define BR_DDR_CR20_CKSRE    (HW_DDR_CR20.B.CKSRE)
#endif

//! @brief Format value for bitfield DDR_CR20_CKSRE.
#define BF_DDR_CR20_CKSRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR20_CKSRE), uint32_t) & BM_DDR_CR20_CKSRE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CKSRE field to a new value.
#define BW_DDR_CR20_CKSRE(v) (HW_DDR_CR20_WR((HW_DDR_CR20_RD() & ~BM_DDR_CR20_CKSRE) | BF_DDR_CR20_CKSRE(v)))
#endif
//@}

/*!
 * @name Register DDR_CR20, field CKSRX[19:16] (RW)
 *
 * Clock stable delay on self refresh exit. Sets the number of cycles to hold
 * the clock stable before exiting self-refresh mode. The clock will run for a
 * minimum of cksrx cycles before CLK rises.
 */
//@{
#define BP_DDR_CR20_CKSRX    (16U)         //!< Bit position for DDR_CR20_CKSRX.
#define BM_DDR_CR20_CKSRX    (0x000F0000U) //!< Bit mask for DDR_CR20_CKSRX.
#define BS_DDR_CR20_CKSRX    (4U)          //!< Bit field size in bits for DDR_CR20_CKSRX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR20_CKSRX field.
#define BR_DDR_CR20_CKSRX    (HW_DDR_CR20.B.CKSRX)
#endif

//! @brief Format value for bitfield DDR_CR20_CKSRX.
#define BF_DDR_CR20_CKSRX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR20_CKSRX), uint32_t) & BM_DDR_CR20_CKSRX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CKSRX field to a new value.
#define BW_DDR_CR20_CKSRX(v) (HW_DDR_CR20_WR((HW_DDR_CR20_RD() & ~BM_DDR_CR20_CKSRX) | BF_DDR_CR20_CKSRX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR20, field WRMD[24] (WO)
 *
 * Write mode register data to the DRAMs. The mode registers are automatically
 * written at initialization of the memory controller. There is no need to
 * initiate a mode register write after setting CR00[START], unless the values in these
 * registers needs to be changed after initialization. This parameter may not be
 * changed when the memory is in power-down mode (CLK is negated). 0 No write
 * occurs 1 Write the mode parameters (EMRS register) in the DRAM devices. This
 * parameter always reads zero.
 */
//@{
#define BP_DDR_CR20_WRMD     (24U)         //!< Bit position for DDR_CR20_WRMD.
#define BM_DDR_CR20_WRMD     (0x01000000U) //!< Bit mask for DDR_CR20_WRMD.
#define BS_DDR_CR20_WRMD     (1U)          //!< Bit field size in bits for DDR_CR20_WRMD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR20_WRMD field.
#define BR_DDR_CR20_WRMD     (BITBAND_ACCESS32(HW_DDR_CR20_ADDR, BP_DDR_CR20_WRMD))
#endif

//! @brief Format value for bitfield DDR_CR20_WRMD.
#define BF_DDR_CR20_WRMD(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR20_WRMD), uint32_t) & BM_DDR_CR20_WRMD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRMD field to a new value.
#define BW_DDR_CR20_WRMD(v)  (BITBAND_ACCESS32(HW_DDR_CR20_ADDR, BP_DDR_CR20_WRMD) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR21 - DDR Control Register 21
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR21 - DDR Control Register 21 (RW)
 *
 * Reset value: 0x00000400U
 */
typedef union _hw_ddr_cr21
{
    uint32_t U;
    struct _hw_ddr_cr21_bitfields
    {
        uint32_t MR0DAT0 : 16;         //!< [15:0]
        uint32_t MR1DAT0 : 16;         //!< [31:16]
    } B;
} hw_ddr_cr21_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR21 register
 */
//@{
#define HW_DDR_CR21_ADDR         (REGS_DDR_BASE + 0x54U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR21              (*(__IO hw_ddr_cr21_t *) HW_DDR_CR21_ADDR)
#define HW_DDR_CR21_RD()         (HW_DDR_CR21.U)
#define HW_DDR_CR21_WR(v)        (HW_DDR_CR21.U = (v))
#define HW_DDR_CR21_SET(v)       (HW_DDR_CR21_WR(HW_DDR_CR21_RD() |  (v)))
#define HW_DDR_CR21_CLR(v)       (HW_DDR_CR21_WR(HW_DDR_CR21_RD() & ~(v)))
#define HW_DDR_CR21_TOG(v)       (HW_DDR_CR21_WR(HW_DDR_CR21_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR21 bitfields
 */

/*!
 * @name Register DDR_CR21, field MR0DAT0[15:0] (RW)
 *
 * Data to program into memory mode register 0 for chip select .
 */
//@{
#define BP_DDR_CR21_MR0DAT0  (0U)          //!< Bit position for DDR_CR21_MR0DAT0.
#define BM_DDR_CR21_MR0DAT0  (0x0000FFFFU) //!< Bit mask for DDR_CR21_MR0DAT0.
#define BS_DDR_CR21_MR0DAT0  (16U)         //!< Bit field size in bits for DDR_CR21_MR0DAT0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR21_MR0DAT0 field.
#define BR_DDR_CR21_MR0DAT0  (HW_DDR_CR21.B.MR0DAT0)
#endif

//! @brief Format value for bitfield DDR_CR21_MR0DAT0.
#define BF_DDR_CR21_MR0DAT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR21_MR0DAT0), uint32_t) & BM_DDR_CR21_MR0DAT0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MR0DAT0 field to a new value.
#define BW_DDR_CR21_MR0DAT0(v) (HW_DDR_CR21_WR((HW_DDR_CR21_RD() & ~BM_DDR_CR21_MR0DAT0) | BF_DDR_CR21_MR0DAT0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR21, field MR1DAT0[31:16] (RW)
 *
 * Data to program into memory mode register 1 for chip select .
 */
//@{
#define BP_DDR_CR21_MR1DAT0  (16U)         //!< Bit position for DDR_CR21_MR1DAT0.
#define BM_DDR_CR21_MR1DAT0  (0xFFFF0000U) //!< Bit mask for DDR_CR21_MR1DAT0.
#define BS_DDR_CR21_MR1DAT0  (16U)         //!< Bit field size in bits for DDR_CR21_MR1DAT0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR21_MR1DAT0 field.
#define BR_DDR_CR21_MR1DAT0  (HW_DDR_CR21.B.MR1DAT0)
#endif

//! @brief Format value for bitfield DDR_CR21_MR1DAT0.
#define BF_DDR_CR21_MR1DAT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR21_MR1DAT0), uint32_t) & BM_DDR_CR21_MR1DAT0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MR1DAT0 field to a new value.
#define BW_DDR_CR21_MR1DAT0(v) (HW_DDR_CR21_WR((HW_DDR_CR21_RD() & ~BM_DDR_CR21_MR1DAT0) | BF_DDR_CR21_MR1DAT0(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR22 - DDR Control Register 22
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR22 - DDR Control Register 22 (RW)
 *
 * Reset value: 0x00000400U
 */
typedef union _hw_ddr_cr22
{
    uint32_t U;
    struct _hw_ddr_cr22_bitfields
    {
        uint32_t MR2DATA0 : 16;        //!< [15:0]
        uint32_t MR3DAT0 : 16;         //!< [31:16]
    } B;
} hw_ddr_cr22_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR22 register
 */
//@{
#define HW_DDR_CR22_ADDR         (REGS_DDR_BASE + 0x58U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR22              (*(__IO hw_ddr_cr22_t *) HW_DDR_CR22_ADDR)
#define HW_DDR_CR22_RD()         (HW_DDR_CR22.U)
#define HW_DDR_CR22_WR(v)        (HW_DDR_CR22.U = (v))
#define HW_DDR_CR22_SET(v)       (HW_DDR_CR22_WR(HW_DDR_CR22_RD() |  (v)))
#define HW_DDR_CR22_CLR(v)       (HW_DDR_CR22_WR(HW_DDR_CR22_RD() & ~(v)))
#define HW_DDR_CR22_TOG(v)       (HW_DDR_CR22_WR(HW_DDR_CR22_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR22 bitfields
 */

/*!
 * @name Register DDR_CR22, field MR2DATA0[15:0] (RW)
 *
 * Data to program into memory mode register 2 for chip select .
 */
//@{
#define BP_DDR_CR22_MR2DATA0 (0U)          //!< Bit position for DDR_CR22_MR2DATA0.
#define BM_DDR_CR22_MR2DATA0 (0x0000FFFFU) //!< Bit mask for DDR_CR22_MR2DATA0.
#define BS_DDR_CR22_MR2DATA0 (16U)         //!< Bit field size in bits for DDR_CR22_MR2DATA0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR22_MR2DATA0 field.
#define BR_DDR_CR22_MR2DATA0 (HW_DDR_CR22.B.MR2DATA0)
#endif

//! @brief Format value for bitfield DDR_CR22_MR2DATA0.
#define BF_DDR_CR22_MR2DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR22_MR2DATA0), uint32_t) & BM_DDR_CR22_MR2DATA0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MR2DATA0 field to a new value.
#define BW_DDR_CR22_MR2DATA0(v) (HW_DDR_CR22_WR((HW_DDR_CR22_RD() & ~BM_DDR_CR22_MR2DATA0) | BF_DDR_CR22_MR2DATA0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR22, field MR3DAT0[31:16] (RW)
 *
 * Data to program into memory mode register 3 for chip select .
 */
//@{
#define BP_DDR_CR22_MR3DAT0  (16U)         //!< Bit position for DDR_CR22_MR3DAT0.
#define BM_DDR_CR22_MR3DAT0  (0xFFFF0000U) //!< Bit mask for DDR_CR22_MR3DAT0.
#define BS_DDR_CR22_MR3DAT0  (16U)         //!< Bit field size in bits for DDR_CR22_MR3DAT0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR22_MR3DAT0 field.
#define BR_DDR_CR22_MR3DAT0  (HW_DDR_CR22.B.MR3DAT0)
#endif

//! @brief Format value for bitfield DDR_CR22_MR3DAT0.
#define BF_DDR_CR22_MR3DAT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR22_MR3DAT0), uint32_t) & BM_DDR_CR22_MR3DAT0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the MR3DAT0 field to a new value.
#define BW_DDR_CR22_MR3DAT0(v) (HW_DDR_CR22_WR((HW_DDR_CR22_RD() & ~BM_DDR_CR22_MR3DAT0) | BF_DDR_CR22_MR3DAT0(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR23 - DDR Control Register 23
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR23 - DDR Control Register 23 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr23
{
    uint32_t U;
    struct _hw_ddr_cr23_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr23_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR23 register
 */
//@{
#define HW_DDR_CR23_ADDR         (REGS_DDR_BASE + 0x5CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR23              (*(__I hw_ddr_cr23_t *) HW_DDR_CR23_ADDR)
#define HW_DDR_CR23_RD()         (HW_DDR_CR23.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR23 bitfields
 */

/*!
 * @name Register DDR_CR23, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR23_Not_Used (0U)          //!< Bit position for DDR_CR23_Not_Used.
#define BM_DDR_CR23_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR23_Not_Used.
#define BS_DDR_CR23_Not_Used (16U)         //!< Bit field size in bits for DDR_CR23_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR23_Not_Used field.
#define BR_DDR_CR23_Not_Used (HW_DDR_CR23.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR23, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR23_NOT_USED (16U)         //!< Bit position for DDR_CR23_NOT_USED.
#define BM_DDR_CR23_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR23_NOT_USED.
#define BS_DDR_CR23_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR23_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR23_NOT_USED field.
#define BR_DDR_CR23_NOT_USED (HW_DDR_CR23.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR24 - DDR Control Register 24
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR24 - DDR Control Register 24 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr24
{
    uint32_t U;
    struct _hw_ddr_cr24_bitfields
    {
        uint32_t RESERVED0 : 32;       //!< [31:0]
    } B;
} hw_ddr_cr24_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR24 register
 */
//@{
#define HW_DDR_CR24_ADDR         (REGS_DDR_BASE + 0x60U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR24              (*(__I hw_ddr_cr24_t *) HW_DDR_CR24_ADDR)
#define HW_DDR_CR24_RD()         (HW_DDR_CR24.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR24 bitfields
 */

//-------------------------------------------------------------------------------------------
// HW_DDR_CR25 - DDR Control Register 25
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR25 - DDR Control Register 25 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr25
{
    uint32_t U;
    struct _hw_ddr_cr25_bitfields
    {
        uint32_t BNK8 : 1;             //!< [0] Eight Bank Mode
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t ADDPINS : 3;          //!< [10:8] Address Pins
        uint32_t RESERVED1 : 5;        //!< [15:11] Reserved
        uint32_t COLSIZ : 3;           //!< [18:16] Column Size
        uint32_t RESERVED2 : 5;        //!< [23:19] Reserved
        uint32_t APREBIT : 4;          //!< [27:24] Auto Precharge Bit
        uint32_t RESERVED3 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr25_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR25 register
 */
//@{
#define HW_DDR_CR25_ADDR         (REGS_DDR_BASE + 0x64U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR25              (*(__IO hw_ddr_cr25_t *) HW_DDR_CR25_ADDR)
#define HW_DDR_CR25_RD()         (HW_DDR_CR25.U)
#define HW_DDR_CR25_WR(v)        (HW_DDR_CR25.U = (v))
#define HW_DDR_CR25_SET(v)       (HW_DDR_CR25_WR(HW_DDR_CR25_RD() |  (v)))
#define HW_DDR_CR25_CLR(v)       (HW_DDR_CR25_WR(HW_DDR_CR25_RD() & ~(v)))
#define HW_DDR_CR25_TOG(v)       (HW_DDR_CR25_WR(HW_DDR_CR25_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR25 bitfields
 */

/*!
 * @name Register DDR_CR25, field BNK8[0] (RW)
 *
 * Number of banks on the DRAMs.
 *
 * Values:
 * - 0 - 4 banks
 * - 1 - 8 banks
 */
//@{
#define BP_DDR_CR25_BNK8     (0U)          //!< Bit position for DDR_CR25_BNK8.
#define BM_DDR_CR25_BNK8     (0x00000001U) //!< Bit mask for DDR_CR25_BNK8.
#define BS_DDR_CR25_BNK8     (1U)          //!< Bit field size in bits for DDR_CR25_BNK8.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR25_BNK8 field.
#define BR_DDR_CR25_BNK8     (BITBAND_ACCESS32(HW_DDR_CR25_ADDR, BP_DDR_CR25_BNK8))
#endif

//! @brief Format value for bitfield DDR_CR25_BNK8.
#define BF_DDR_CR25_BNK8(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR25_BNK8), uint32_t) & BM_DDR_CR25_BNK8)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BNK8 field to a new value.
#define BW_DDR_CR25_BNK8(v)  (BITBAND_ACCESS32(HW_DDR_CR25_ADDR, BP_DDR_CR25_BNK8) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR25, field ADDPINS[10:8] (RW)
 *
 * Defines the difference between the maximum number of address pins configured
 * (16) and the actual number of pins used. The user address is automatically
 * shifted so that the user address space is mapped contiguously into the memory map
 * based on the value of this parameter. For details, refer to section "DDR
 * SDRAM Address Mapping Options".
 */
//@{
#define BP_DDR_CR25_ADDPINS  (8U)          //!< Bit position for DDR_CR25_ADDPINS.
#define BM_DDR_CR25_ADDPINS  (0x00000700U) //!< Bit mask for DDR_CR25_ADDPINS.
#define BS_DDR_CR25_ADDPINS  (3U)          //!< Bit field size in bits for DDR_CR25_ADDPINS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR25_ADDPINS field.
#define BR_DDR_CR25_ADDPINS  (HW_DDR_CR25.B.ADDPINS)
#endif

//! @brief Format value for bitfield DDR_CR25_ADDPINS.
#define BF_DDR_CR25_ADDPINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR25_ADDPINS), uint32_t) & BM_DDR_CR25_ADDPINS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDPINS field to a new value.
#define BW_DDR_CR25_ADDPINS(v) (HW_DDR_CR25_WR((HW_DDR_CR25_RD() & ~BM_DDR_CR25_ADDPINS) | BF_DDR_CR25_ADDPINS(v)))
#endif
//@}

/*!
 * @name Register DDR_CR25, field COLSIZ[18:16] (RW)
 *
 * Difference between the 11 column pins available and the number being used.
 * The user address is automatically shifted so that the user address space is
 * mapped contiguously into the memory map based on the value of this parameter. For
 * details, refer to section "DDR SDRAM Address Mapping Options".
 */
//@{
#define BP_DDR_CR25_COLSIZ   (16U)         //!< Bit position for DDR_CR25_COLSIZ.
#define BM_DDR_CR25_COLSIZ   (0x00070000U) //!< Bit mask for DDR_CR25_COLSIZ.
#define BS_DDR_CR25_COLSIZ   (3U)          //!< Bit field size in bits for DDR_CR25_COLSIZ.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR25_COLSIZ field.
#define BR_DDR_CR25_COLSIZ   (HW_DDR_CR25.B.COLSIZ)
#endif

//! @brief Format value for bitfield DDR_CR25_COLSIZ.
#define BF_DDR_CR25_COLSIZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR25_COLSIZ), uint32_t) & BM_DDR_CR25_COLSIZ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the COLSIZ field to a new value.
#define BW_DDR_CR25_COLSIZ(v) (HW_DDR_CR25_WR((HW_DDR_CR25_RD() & ~BM_DDR_CR25_COLSIZ) | BF_DDR_CR25_COLSIZ(v)))
#endif
//@}

/*!
 * @name Register DDR_CR25, field APREBIT[27:24] (RW)
 *
 * Location of the auto precharge bit in the DRAM address in decimal encoding.
 */
//@{
#define BP_DDR_CR25_APREBIT  (24U)         //!< Bit position for DDR_CR25_APREBIT.
#define BM_DDR_CR25_APREBIT  (0x0F000000U) //!< Bit mask for DDR_CR25_APREBIT.
#define BS_DDR_CR25_APREBIT  (4U)          //!< Bit field size in bits for DDR_CR25_APREBIT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR25_APREBIT field.
#define BR_DDR_CR25_APREBIT  (HW_DDR_CR25.B.APREBIT)
#endif

//! @brief Format value for bitfield DDR_CR25_APREBIT.
#define BF_DDR_CR25_APREBIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR25_APREBIT), uint32_t) & BM_DDR_CR25_APREBIT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the APREBIT field to a new value.
#define BW_DDR_CR25_APREBIT(v) (HW_DDR_CR25_WR((HW_DDR_CR25_RD() & ~BM_DDR_CR25_APREBIT) | BF_DDR_CR25_APREBIT(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR26 - DDR Control Register 26
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR26 - DDR Control Register 26 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr26
{
    uint32_t U;
    struct _hw_ddr_cr26_bitfields
    {
        uint32_t AGECNT : 8;           //!< [7:0] Age Count
        uint32_t CMDAGE : 8;           //!< [15:8] Command Age count
        uint32_t ADDCOL : 1;           //!< [16] Address Collision enable
        uint32_t RESERVED0 : 7;        //!< [23:17] Reserved
        uint32_t BNKSPT : 1;           //!< [24] Bank Split enable
        uint32_t RESERVED1 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr26_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR26 register
 */
//@{
#define HW_DDR_CR26_ADDR         (REGS_DDR_BASE + 0x68U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR26              (*(__IO hw_ddr_cr26_t *) HW_DDR_CR26_ADDR)
#define HW_DDR_CR26_RD()         (HW_DDR_CR26.U)
#define HW_DDR_CR26_WR(v)        (HW_DDR_CR26.U = (v))
#define HW_DDR_CR26_SET(v)       (HW_DDR_CR26_WR(HW_DDR_CR26_RD() |  (v)))
#define HW_DDR_CR26_CLR(v)       (HW_DDR_CR26_WR(HW_DDR_CR26_RD() & ~(v)))
#define HW_DDR_CR26_TOG(v)       (HW_DDR_CR26_WR(HW_DDR_CR26_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR26 bitfields
 */

/*!
 * @name Register DDR_CR26, field AGECNT[7:0] (RW)
 *
 * Initial value of master aging-rate counter for command aging. When using the
 * placement logic to fill the command queue, the command aging counters are
 * decremented one each time the master aging-rate counter counts down AGECNT cycles.
 */
//@{
#define BP_DDR_CR26_AGECNT   (0U)          //!< Bit position for DDR_CR26_AGECNT.
#define BM_DDR_CR26_AGECNT   (0x000000FFU) //!< Bit mask for DDR_CR26_AGECNT.
#define BS_DDR_CR26_AGECNT   (8U)          //!< Bit field size in bits for DDR_CR26_AGECNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR26_AGECNT field.
#define BR_DDR_CR26_AGECNT   (HW_DDR_CR26.B.AGECNT)
#endif

//! @brief Format value for bitfield DDR_CR26_AGECNT.
#define BF_DDR_CR26_AGECNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR26_AGECNT), uint32_t) & BM_DDR_CR26_AGECNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the AGECNT field to a new value.
#define BW_DDR_CR26_AGECNT(v) (HW_DDR_CR26_WR((HW_DDR_CR26_RD() & ~BM_DDR_CR26_AGECNT) | BF_DDR_CR26_AGECNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR26, field CMDAGE[15:8] (RW)
 *
 * Initial value of individual command aging counters associated with each
 * command in the command queue. When using the placement logic to fill the command
 * queue, the command aging counters decrement one each time the master aging-rate
 * counter counts down CR26[AGECNT] cycles.
 */
//@{
#define BP_DDR_CR26_CMDAGE   (8U)          //!< Bit position for DDR_CR26_CMDAGE.
#define BM_DDR_CR26_CMDAGE   (0x0000FF00U) //!< Bit mask for DDR_CR26_CMDAGE.
#define BS_DDR_CR26_CMDAGE   (8U)          //!< Bit field size in bits for DDR_CR26_CMDAGE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR26_CMDAGE field.
#define BR_DDR_CR26_CMDAGE   (HW_DDR_CR26.B.CMDAGE)
#endif

//! @brief Format value for bitfield DDR_CR26_CMDAGE.
#define BF_DDR_CR26_CMDAGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR26_CMDAGE), uint32_t) & BM_DDR_CR26_CMDAGE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CMDAGE field to a new value.
#define BW_DDR_CR26_CMDAGE(v) (HW_DDR_CR26_WR((HW_DDR_CR26_RD() & ~BM_DDR_CR26_CMDAGE) | BF_DDR_CR26_CMDAGE(v)))
#endif
//@}

/*!
 * @name Register DDR_CR26, field ADDCOL[16] (RW)
 *
 * Enables address collision/data coherency detection as a condition when using
 * the placement logic to fill the command queue.
 *
 * Values:
 * - 0 - Disable
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR26_ADDCOL   (16U)         //!< Bit position for DDR_CR26_ADDCOL.
#define BM_DDR_CR26_ADDCOL   (0x00010000U) //!< Bit mask for DDR_CR26_ADDCOL.
#define BS_DDR_CR26_ADDCOL   (1U)          //!< Bit field size in bits for DDR_CR26_ADDCOL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR26_ADDCOL field.
#define BR_DDR_CR26_ADDCOL   (BITBAND_ACCESS32(HW_DDR_CR26_ADDR, BP_DDR_CR26_ADDCOL))
#endif

//! @brief Format value for bitfield DDR_CR26_ADDCOL.
#define BF_DDR_CR26_ADDCOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR26_ADDCOL), uint32_t) & BM_DDR_CR26_ADDCOL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ADDCOL field to a new value.
#define BW_DDR_CR26_ADDCOL(v) (BITBAND_ACCESS32(HW_DDR_CR26_ADDR, BP_DDR_CR26_ADDCOL) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR26, field BNKSPT[24] (RW)
 *
 * For command queue placement logic.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR26_BNKSPT   (24U)         //!< Bit position for DDR_CR26_BNKSPT.
#define BM_DDR_CR26_BNKSPT   (0x01000000U) //!< Bit mask for DDR_CR26_BNKSPT.
#define BS_DDR_CR26_BNKSPT   (1U)          //!< Bit field size in bits for DDR_CR26_BNKSPT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR26_BNKSPT field.
#define BR_DDR_CR26_BNKSPT   (BITBAND_ACCESS32(HW_DDR_CR26_ADDR, BP_DDR_CR26_BNKSPT))
#endif

//! @brief Format value for bitfield DDR_CR26_BNKSPT.
#define BF_DDR_CR26_BNKSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR26_BNKSPT), uint32_t) & BM_DDR_CR26_BNKSPT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BNKSPT field to a new value.
#define BW_DDR_CR26_BNKSPT(v) (BITBAND_ACCESS32(HW_DDR_CR26_ADDR, BP_DDR_CR26_BNKSPT) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR27 - DDR Control Register 27
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR27 - DDR Control Register 27 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr27
{
    uint32_t U;
    struct _hw_ddr_cr27_bitfields
    {
        uint32_t PLEN : 1;             //!< [0] Placement Enable
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t PRIEN : 1;            //!< [8] Priority Enable
        uint32_t RESERVED1 : 7;        //!< [15:9] Reserved
        uint32_t RWEN : 1;             //!< [16] Read Write same Enable
        uint32_t RESERVED2 : 7;        //!< [23:17] Reserved
        uint32_t SWPEN : 1;            //!< [24] Swap Enable
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr27_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR27 register
 */
//@{
#define HW_DDR_CR27_ADDR         (REGS_DDR_BASE + 0x6CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR27              (*(__IO hw_ddr_cr27_t *) HW_DDR_CR27_ADDR)
#define HW_DDR_CR27_RD()         (HW_DDR_CR27.U)
#define HW_DDR_CR27_WR(v)        (HW_DDR_CR27.U = (v))
#define HW_DDR_CR27_SET(v)       (HW_DDR_CR27_WR(HW_DDR_CR27_RD() |  (v)))
#define HW_DDR_CR27_CLR(v)       (HW_DDR_CR27_WR(HW_DDR_CR27_RD() & ~(v)))
#define HW_DDR_CR27_TOG(v)       (HW_DDR_CR27_WR(HW_DDR_CR27_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR27 bitfields
 */

/*!
 * @name Register DDR_CR27, field PLEN[0] (RW)
 *
 * Enable placement logic to fill the command queue.
 *
 * Values:
 * - 0 - Disabled. The command queue is a straight FIFO.
 * - 1 - Enabled. The command queue is filled according to the placement logic
 *     factors.
 */
//@{
#define BP_DDR_CR27_PLEN     (0U)          //!< Bit position for DDR_CR27_PLEN.
#define BM_DDR_CR27_PLEN     (0x00000001U) //!< Bit mask for DDR_CR27_PLEN.
#define BS_DDR_CR27_PLEN     (1U)          //!< Bit field size in bits for DDR_CR27_PLEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR27_PLEN field.
#define BR_DDR_CR27_PLEN     (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_PLEN))
#endif

//! @brief Format value for bitfield DDR_CR27_PLEN.
#define BF_DDR_CR27_PLEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR27_PLEN), uint32_t) & BM_DDR_CR27_PLEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PLEN field to a new value.
#define BW_DDR_CR27_PLEN(v)  (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_PLEN) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR27, field PRIEN[8] (RW)
 *
 * Enable priority for command queue placement logic.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR27_PRIEN    (8U)          //!< Bit position for DDR_CR27_PRIEN.
#define BM_DDR_CR27_PRIEN    (0x00000100U) //!< Bit mask for DDR_CR27_PRIEN.
#define BS_DDR_CR27_PRIEN    (1U)          //!< Bit field size in bits for DDR_CR27_PRIEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR27_PRIEN field.
#define BR_DDR_CR27_PRIEN    (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_PRIEN))
#endif

//! @brief Format value for bitfield DDR_CR27_PRIEN.
#define BF_DDR_CR27_PRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR27_PRIEN), uint32_t) & BM_DDR_CR27_PRIEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PRIEN field to a new value.
#define BW_DDR_CR27_PRIEN(v) (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_PRIEN) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR27, field RWEN[16] (RW)
 *
 * Enable read/write grouping for command queue placement logic.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR27_RWEN     (16U)         //!< Bit position for DDR_CR27_RWEN.
#define BM_DDR_CR27_RWEN     (0x00010000U) //!< Bit mask for DDR_CR27_RWEN.
#define BS_DDR_CR27_RWEN     (1U)          //!< Bit field size in bits for DDR_CR27_RWEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR27_RWEN field.
#define BR_DDR_CR27_RWEN     (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_RWEN))
#endif

//! @brief Format value for bitfield DDR_CR27_RWEN.
#define BF_DDR_CR27_RWEN(v)  (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR27_RWEN), uint32_t) & BM_DDR_CR27_RWEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RWEN field to a new value.
#define BW_DDR_CR27_RWEN(v)  (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_RWEN) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR27, field SWPEN[24] (RW)
 *
 * Enables swapping of the active command for a new higher-priority command when
 * using the placement logic.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR27_SWPEN    (24U)         //!< Bit position for DDR_CR27_SWPEN.
#define BM_DDR_CR27_SWPEN    (0x01000000U) //!< Bit mask for DDR_CR27_SWPEN.
#define BS_DDR_CR27_SWPEN    (1U)          //!< Bit field size in bits for DDR_CR27_SWPEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR27_SWPEN field.
#define BR_DDR_CR27_SWPEN    (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_SWPEN))
#endif

//! @brief Format value for bitfield DDR_CR27_SWPEN.
#define BF_DDR_CR27_SWPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR27_SWPEN), uint32_t) & BM_DDR_CR27_SWPEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SWPEN field to a new value.
#define BW_DDR_CR27_SWPEN(v) (BITBAND_ACCESS32(HW_DDR_CR27_ADDR, BP_DDR_CR27_SWPEN) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR28 - DDR Control Register 28
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR28 - DDR Control Register 28 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr28
{
    uint32_t U;
    struct _hw_ddr_cr28_bitfields
    {
        uint32_t CSMAP : 1;            //!< [0] Chip Select Map
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t REDUC : 1;            //!< [8]
        uint32_t RESERVED1 : 7;        //!< [15:9] Reserved
        uint32_t BIGEND : 1;           //!< [16] Big Endian Enable
        uint32_t RESERVED2 : 7;        //!< [23:17] Reserved
        uint32_t CMDLATR : 1;          //!< [24] Command Latency Reduction Enable
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr28_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR28 register
 */
//@{
#define HW_DDR_CR28_ADDR         (REGS_DDR_BASE + 0x70U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR28              (*(__IO hw_ddr_cr28_t *) HW_DDR_CR28_ADDR)
#define HW_DDR_CR28_RD()         (HW_DDR_CR28.U)
#define HW_DDR_CR28_WR(v)        (HW_DDR_CR28.U = (v))
#define HW_DDR_CR28_SET(v)       (HW_DDR_CR28_WR(HW_DDR_CR28_RD() |  (v)))
#define HW_DDR_CR28_CLR(v)       (HW_DDR_CR28_WR(HW_DDR_CR28_RD() & ~(v)))
#define HW_DDR_CR28_TOG(v)       (HW_DDR_CR28_WR(HW_DDR_CR28_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR28 bitfields
 */

/*!
 * @name Register DDR_CR28, field CSMAP[0] (RW)
 *
 * Defines if the chip select is enabled. 0 Chip select disabled 1 Chip select
 * enabled
 */
//@{
#define BP_DDR_CR28_CSMAP    (0U)          //!< Bit position for DDR_CR28_CSMAP.
#define BM_DDR_CR28_CSMAP    (0x00000001U) //!< Bit mask for DDR_CR28_CSMAP.
#define BS_DDR_CR28_CSMAP    (1U)          //!< Bit field size in bits for DDR_CR28_CSMAP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR28_CSMAP field.
#define BR_DDR_CR28_CSMAP    (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_CSMAP))
#endif

//! @brief Format value for bitfield DDR_CR28_CSMAP.
#define BF_DDR_CR28_CSMAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR28_CSMAP), uint32_t) & BM_DDR_CR28_CSMAP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CSMAP field to a new value.
#define BW_DDR_CR28_CSMAP(v) (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_CSMAP) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR28, field REDUC[8] (RW)
 *
 * Controls the width of the memory datapath. The entire user datapath is used
 * regardless of this setting. When operating in half datapath mode, only burst
 * length value of 4 and 8 are supported.
 *
 * Values:
 * - 0 - 16-bit - standard operation using full memory bus
 * - 1 - 8-bit - Memory datapath width is half of the maximum size. The upper
 *     half of the memory busses (DQ, DQS, and DM) are unused and relevant data
 *     only exists in the lower half of the busses.
 */
//@{
#define BP_DDR_CR28_REDUC    (8U)          //!< Bit position for DDR_CR28_REDUC.
#define BM_DDR_CR28_REDUC    (0x00000100U) //!< Bit mask for DDR_CR28_REDUC.
#define BS_DDR_CR28_REDUC    (1U)          //!< Bit field size in bits for DDR_CR28_REDUC.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR28_REDUC field.
#define BR_DDR_CR28_REDUC    (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_REDUC))
#endif

//! @brief Format value for bitfield DDR_CR28_REDUC.
#define BF_DDR_CR28_REDUC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR28_REDUC), uint32_t) & BM_DDR_CR28_REDUC)

#ifndef __LANGUAGE_ASM__
//! @brief Set the REDUC field to a new value.
#define BW_DDR_CR28_REDUC(v) (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_REDUC) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR28, field BIGEND[16] (RW)
 *
 * Set byte ordering as little endian or big endian.
 *
 * Values:
 * - 0 - Little endian
 * - 1 - Big endian
 */
//@{
#define BP_DDR_CR28_BIGEND   (16U)         //!< Bit position for DDR_CR28_BIGEND.
#define BM_DDR_CR28_BIGEND   (0x00010000U) //!< Bit mask for DDR_CR28_BIGEND.
#define BS_DDR_CR28_BIGEND   (1U)          //!< Bit field size in bits for DDR_CR28_BIGEND.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR28_BIGEND field.
#define BR_DDR_CR28_BIGEND   (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_BIGEND))
#endif

//! @brief Format value for bitfield DDR_CR28_BIGEND.
#define BF_DDR_CR28_BIGEND(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR28_BIGEND), uint32_t) & BM_DDR_CR28_BIGEND)

#ifndef __LANGUAGE_ASM__
//! @brief Set the BIGEND field to a new value.
#define BW_DDR_CR28_BIGEND(v) (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_BIGEND) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR28, field CMDLATR[24] (RW)
 *
 * Enable latency reduction within I/O cells of the PHY.
 *
 * Values:
 * - 0 - Disable
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR28_CMDLATR  (24U)         //!< Bit position for DDR_CR28_CMDLATR.
#define BM_DDR_CR28_CMDLATR  (0x01000000U) //!< Bit mask for DDR_CR28_CMDLATR.
#define BS_DDR_CR28_CMDLATR  (1U)          //!< Bit field size in bits for DDR_CR28_CMDLATR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR28_CMDLATR field.
#define BR_DDR_CR28_CMDLATR  (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_CMDLATR))
#endif

//! @brief Format value for bitfield DDR_CR28_CMDLATR.
#define BF_DDR_CR28_CMDLATR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR28_CMDLATR), uint32_t) & BM_DDR_CR28_CMDLATR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CMDLATR field to a new value.
#define BW_DDR_CR28_CMDLATR(v) (BITBAND_ACCESS32(HW_DDR_CR28_ADDR, BP_DDR_CR28_CMDLATR) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR29 - DDR Control Register 29
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR29 - DDR Control Register 29 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr29
{
    uint32_t U;
    struct _hw_ddr_cr29_bitfields
    {
        uint32_t WRLATR : 1;           //!< [0] Write Latency Reduction enable
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t FSTWR : 1;            //!< [8] Fast Write
        uint32_t RESERVED1 : 7;        //!< [15:9] Reserved
        uint32_t QFULL : 2;            //!< [17:16] Queue Fullness
        uint32_t RESERVED2 : 6;        //!< [23:18] Reserved
        uint32_t RESYNC : 1;           //!< [24] Resyncronize
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr29_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR29 register
 */
//@{
#define HW_DDR_CR29_ADDR         (REGS_DDR_BASE + 0x74U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR29              (*(__IO hw_ddr_cr29_t *) HW_DDR_CR29_ADDR)
#define HW_DDR_CR29_RD()         (HW_DDR_CR29.U)
#define HW_DDR_CR29_WR(v)        (HW_DDR_CR29.U = (v))
#define HW_DDR_CR29_SET(v)       (HW_DDR_CR29_WR(HW_DDR_CR29_RD() |  (v)))
#define HW_DDR_CR29_CLR(v)       (HW_DDR_CR29_WR(HW_DDR_CR29_RD() & ~(v)))
#define HW_DDR_CR29_TOG(v)       (HW_DDR_CR29_WR(HW_DDR_CR29_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR29 bitfields
 */

/*!
 * @name Register DDR_CR29, field WRLATR[0] (RW)
 *
 * Enable latency reduction in data path within the I/O cells of the PHY.
 *
 * Values:
 * - 0 - Disable
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR29_WRLATR   (0U)          //!< Bit position for DDR_CR29_WRLATR.
#define BM_DDR_CR29_WRLATR   (0x00000001U) //!< Bit mask for DDR_CR29_WRLATR.
#define BS_DDR_CR29_WRLATR   (1U)          //!< Bit field size in bits for DDR_CR29_WRLATR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR29_WRLATR field.
#define BR_DDR_CR29_WRLATR   (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_WRLATR))
#endif

//! @brief Format value for bitfield DDR_CR29_WRLATR.
#define BF_DDR_CR29_WRLATR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR29_WRLATR), uint32_t) & BM_DDR_CR29_WRLATR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRLATR field to a new value.
#define BW_DDR_CR29_WRLATR(v) (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_WRLATR) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR29, field FSTWR[8] (RW)
 *
 * Defines when write commands are issued to DRAM devices.
 *
 * Values:
 * - 0 - The memory controller issues a write command to the DRAM devices when
 *     it has received enough data for one DRAM burst. Write data can be sent in
 *     any cycle relative to the write command. This mode also allows for
 *     multi-word write command data to arrive in non-sequential cycles.
 * - 1 - The memory controller issues a write command to the DRAM devices after
 *     the first word of the write data is received by the memory controller. The
 *     first word can be sent at any time relative to the write command. In this
 *     mode, multi-word write command data must be available to the memory
 *     controller in sequential cycles.
 */
//@{
#define BP_DDR_CR29_FSTWR    (8U)          //!< Bit position for DDR_CR29_FSTWR.
#define BM_DDR_CR29_FSTWR    (0x00000100U) //!< Bit mask for DDR_CR29_FSTWR.
#define BS_DDR_CR29_FSTWR    (1U)          //!< Bit field size in bits for DDR_CR29_FSTWR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR29_FSTWR field.
#define BR_DDR_CR29_FSTWR    (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_FSTWR))
#endif

//! @brief Format value for bitfield DDR_CR29_FSTWR.
#define BF_DDR_CR29_FSTWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR29_FSTWR), uint32_t) & BM_DDR_CR29_FSTWR)

#ifndef __LANGUAGE_ASM__
//! @brief Set the FSTWR field to a new value.
#define BW_DDR_CR29_FSTWR(v) (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_FSTWR) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR29, field QFULL[17:16] (RW)
 *
 * Defines quantity of data that will be considered full for the command queue.
 * When this value is reached, the g_almost_full signal will be driven to the
 * user interface.
 */
//@{
#define BP_DDR_CR29_QFULL    (16U)         //!< Bit position for DDR_CR29_QFULL.
#define BM_DDR_CR29_QFULL    (0x00030000U) //!< Bit mask for DDR_CR29_QFULL.
#define BS_DDR_CR29_QFULL    (2U)          //!< Bit field size in bits for DDR_CR29_QFULL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR29_QFULL field.
#define BR_DDR_CR29_QFULL    (HW_DDR_CR29.B.QFULL)
#endif

//! @brief Format value for bitfield DDR_CR29_QFULL.
#define BF_DDR_CR29_QFULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR29_QFULL), uint32_t) & BM_DDR_CR29_QFULL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the QFULL field to a new value.
#define BW_DDR_CR29_QFULL(v) (HW_DDR_CR29_WR((HW_DDR_CR29_RD() & ~BM_DDR_CR29_QFULL) | BF_DDR_CR29_QFULL(v)))
#endif
//@}

/*!
 * @name Register DDR_CR29, field RESYNC[24] (WO)
 *
 * Initiate a DLL resync.
 *
 * Values:
 * - 0 - No effect
 * - 1 - Initiate
 */
//@{
#define BP_DDR_CR29_RESYNC   (24U)         //!< Bit position for DDR_CR29_RESYNC.
#define BM_DDR_CR29_RESYNC   (0x01000000U) //!< Bit mask for DDR_CR29_RESYNC.
#define BS_DDR_CR29_RESYNC   (1U)          //!< Bit field size in bits for DDR_CR29_RESYNC.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR29_RESYNC field.
#define BR_DDR_CR29_RESYNC   (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_RESYNC))
#endif

//! @brief Format value for bitfield DDR_CR29_RESYNC.
#define BF_DDR_CR29_RESYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR29_RESYNC), uint32_t) & BM_DDR_CR29_RESYNC)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RESYNC field to a new value.
#define BW_DDR_CR29_RESYNC(v) (BITBAND_ACCESS32(HW_DDR_CR29_ADDR, BP_DDR_CR29_RESYNC) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR30 - DDR Control Register 30
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR30 - DDR Control Register 30 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr30
{
    uint32_t U;
    struct _hw_ddr_cr30_bitfields
    {
        uint32_t RSYNCRF : 1;          //!< [0] Resynchroize after Refresh
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t INTSTAT : 9;          //!< [16:8] Interrupt Status
        uint32_t RESERVED1 : 7;        //!< [23:17] Reserved
        uint32_t INTACK : 8;           //!< [31:24] Interupt Acknowlege
    } B;
} hw_ddr_cr30_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR30 register
 */
//@{
#define HW_DDR_CR30_ADDR         (REGS_DDR_BASE + 0x78U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR30              (*(__IO hw_ddr_cr30_t *) HW_DDR_CR30_ADDR)
#define HW_DDR_CR30_RD()         (HW_DDR_CR30.U)
#define HW_DDR_CR30_WR(v)        (HW_DDR_CR30.U = (v))
#define HW_DDR_CR30_SET(v)       (HW_DDR_CR30_WR(HW_DDR_CR30_RD() |  (v)))
#define HW_DDR_CR30_CLR(v)       (HW_DDR_CR30_WR(HW_DDR_CR30_RD() & ~(v)))
#define HW_DDR_CR30_TOG(v)       (HW_DDR_CR30_WR(HW_DDR_CR30_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR30 bitfields
 */

/*!
 * @name Register DDR_CR30, field RSYNCRF[0] (RW)
 *
 * Enables automatic DLL resync after every refresh.
 *
 * Values:
 * - 0 - No effect
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR30_RSYNCRF  (0U)          //!< Bit position for DDR_CR30_RSYNCRF.
#define BM_DDR_CR30_RSYNCRF  (0x00000001U) //!< Bit mask for DDR_CR30_RSYNCRF.
#define BS_DDR_CR30_RSYNCRF  (1U)          //!< Bit field size in bits for DDR_CR30_RSYNCRF.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR30_RSYNCRF field.
#define BR_DDR_CR30_RSYNCRF  (BITBAND_ACCESS32(HW_DDR_CR30_ADDR, BP_DDR_CR30_RSYNCRF))
#endif

//! @brief Format value for bitfield DDR_CR30_RSYNCRF.
#define BF_DDR_CR30_RSYNCRF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR30_RSYNCRF), uint32_t) & BM_DDR_CR30_RSYNCRF)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RSYNCRF field to a new value.
#define BW_DDR_CR30_RSYNCRF(v) (BITBAND_ACCESS32(HW_DDR_CR30_ADDR, BP_DDR_CR30_RSYNCRF) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR30, field INTSTAT[16:8] (RO)
 *
 * Status of interrupt features in the controller. Bit[16]: Logical OR of
 * INTSTATUS[7:0] Bit[15]: User-initiated DLL resync is finished Bit[14]:
 * dfi_int_complete state change detected Bit[13]: Indicates that a register interface mode
 * register write has finished and that another register interface mode register
 * write may be issued Bit[12]: ODT enabled and CAS Latency 3 programmed error
 * detected. This is an unsupported programming option Bit[11]: Both DDR2 and Mobile
 * modes have been enabled Bit[10]: DRAM initialization complete Bit[9]: Multiple
 * accesses outside the defined physical memory space detected Bit[8]: A single
 * access outside the defined physical memory space detected
 */
//@{
#define BP_DDR_CR30_INTSTAT  (8U)          //!< Bit position for DDR_CR30_INTSTAT.
#define BM_DDR_CR30_INTSTAT  (0x0001FF00U) //!< Bit mask for DDR_CR30_INTSTAT.
#define BS_DDR_CR30_INTSTAT  (9U)          //!< Bit field size in bits for DDR_CR30_INTSTAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR30_INTSTAT field.
#define BR_DDR_CR30_INTSTAT  (HW_DDR_CR30.B.INTSTAT)
#endif
//@}

/*!
 * @name Register DDR_CR30, field INTACK[31:24] (WORZ)
 *
 * Clear the INTSTATUS parameter. This parameter will always read back as 0x0.
 *
 * Values:
 * - 0 - No effect
 * - 1 - Clear the corresponding bit in INTSTATUS
 */
//@{
#define BP_DDR_CR30_INTACK   (24U)         //!< Bit position for DDR_CR30_INTACK.
#define BM_DDR_CR30_INTACK   (0xFF000000U) //!< Bit mask for DDR_CR30_INTACK.
#define BS_DDR_CR30_INTACK   (8U)          //!< Bit field size in bits for DDR_CR30_INTACK.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR30_INTACK field.
#define BR_DDR_CR30_INTACK   (HW_DDR_CR30.B.INTACK)
#endif

//! @brief Format value for bitfield DDR_CR30_INTACK.
#define BF_DDR_CR30_INTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR30_INTACK), uint32_t) & BM_DDR_CR30_INTACK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the INTACK field to a new value.
#define BW_DDR_CR30_INTACK(v) (HW_DDR_CR30_WR((HW_DDR_CR30_RD() & ~BM_DDR_CR30_INTACK) | BF_DDR_CR30_INTACK(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR31 - DDR Control Register 31
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR31 - DDR Control Register 31 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr31
{
    uint32_t U;
    struct _hw_ddr_cr31_bitfields
    {
        uint32_t INTMASK : 9;          //!< [8:0] Interrupt Mask
        uint32_t RESERVED0 : 23;       //!< [31:9] Reserved
    } B;
} hw_ddr_cr31_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR31 register
 */
//@{
#define HW_DDR_CR31_ADDR         (REGS_DDR_BASE + 0x7CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR31              (*(__IO hw_ddr_cr31_t *) HW_DDR_CR31_ADDR)
#define HW_DDR_CR31_RD()         (HW_DDR_CR31.U)
#define HW_DDR_CR31_WR(v)        (HW_DDR_CR31.U = (v))
#define HW_DDR_CR31_SET(v)       (HW_DDR_CR31_WR(HW_DDR_CR31_RD() |  (v)))
#define HW_DDR_CR31_CLR(v)       (HW_DDR_CR31_WR(HW_DDR_CR31_RD() & ~(v)))
#define HW_DDR_CR31_TOG(v)       (HW_DDR_CR31_WR(HW_DDR_CR31_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR31 bitfields
 */

/*!
 * @name Register DDR_CR31, field INTMASK[8:0] (RW)
 *
 * Masks for controller interrupt signals from the INTSTATUS parameter.
 *
 * Values:
 * - 0 - No mask
 * - 1 - Mask corresponding interrupt signal
 */
//@{
#define BP_DDR_CR31_INTMASK  (0U)          //!< Bit position for DDR_CR31_INTMASK.
#define BM_DDR_CR31_INTMASK  (0x000001FFU) //!< Bit mask for DDR_CR31_INTMASK.
#define BS_DDR_CR31_INTMASK  (9U)          //!< Bit field size in bits for DDR_CR31_INTMASK.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR31_INTMASK field.
#define BR_DDR_CR31_INTMASK  (HW_DDR_CR31.B.INTMASK)
#endif

//! @brief Format value for bitfield DDR_CR31_INTMASK.
#define BF_DDR_CR31_INTMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR31_INTMASK), uint32_t) & BM_DDR_CR31_INTMASK)

#ifndef __LANGUAGE_ASM__
//! @brief Set the INTMASK field to a new value.
#define BW_DDR_CR31_INTMASK(v) (HW_DDR_CR31_WR((HW_DDR_CR31_RD() & ~BM_DDR_CR31_INTMASK) | BF_DDR_CR31_INTMASK(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR32 - DDR Control Register 32
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR32 - DDR Control Register 32 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr32
{
    uint32_t U;
    struct _hw_ddr_cr32_bitfields
    {
        uint32_t OORAD : 32;           //!< [31:0] Out Of Range Address
    } B;
} hw_ddr_cr32_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR32 register
 */
//@{
#define HW_DDR_CR32_ADDR         (REGS_DDR_BASE + 0x80U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR32              (*(__I hw_ddr_cr32_t *) HW_DDR_CR32_ADDR)
#define HW_DDR_CR32_RD()         (HW_DDR_CR32.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR32 bitfields
 */

/*!
 * @name Register DDR_CR32, field OORAD[31:0] (RO)
 *
 * Address of the command that caused an out-of-range interrupt.
 */
//@{
#define BP_DDR_CR32_OORAD    (0U)          //!< Bit position for DDR_CR32_OORAD.
#define BM_DDR_CR32_OORAD    (0xFFFFFFFFU) //!< Bit mask for DDR_CR32_OORAD.
#define BS_DDR_CR32_OORAD    (32U)         //!< Bit field size in bits for DDR_CR32_OORAD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR32_OORAD field.
#define BR_DDR_CR32_OORAD    (HW_DDR_CR32.B.OORAD)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR33 - DDR Control Register 33
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR33 - DDR Control Register 33 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr33
{
    uint32_t U;
    struct _hw_ddr_cr33_bitfields
    {
        uint32_t OORLEN : 10;          //!< [9:0] Out Of Range Length
        uint32_t RESERVED0 : 6;        //!< [15:10] Reserved
        uint32_t OORTYP : 6;           //!< [21:16] Out Of Range Type
        uint32_t RESERVED1 : 2;        //!< [23:22] Reserved
        uint32_t OORID : 2;            //!< [25:24] Out Of Range source ID
        uint32_t RESERVED2 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_cr33_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR33 register
 */
//@{
#define HW_DDR_CR33_ADDR         (REGS_DDR_BASE + 0x84U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR33              (*(__I hw_ddr_cr33_t *) HW_DDR_CR33_ADDR)
#define HW_DDR_CR33_RD()         (HW_DDR_CR33.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR33 bitfields
 */

/*!
 * @name Register DDR_CR33, field OORLEN[9:0] (RO)
 *
 * Length of command that caused an out-of-range interrupt request.
 */
//@{
#define BP_DDR_CR33_OORLEN   (0U)          //!< Bit position for DDR_CR33_OORLEN.
#define BM_DDR_CR33_OORLEN   (0x000003FFU) //!< Bit mask for DDR_CR33_OORLEN.
#define BS_DDR_CR33_OORLEN   (10U)         //!< Bit field size in bits for DDR_CR33_OORLEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR33_OORLEN field.
#define BR_DDR_CR33_OORLEN   (HW_DDR_CR33.B.OORLEN)
#endif
//@}

/*!
 * @name Register DDR_CR33, field OORTYP[21:16] (RO)
 *
 * Type of command that caused an out-of-range interrupt request.
 */
//@{
#define BP_DDR_CR33_OORTYP   (16U)         //!< Bit position for DDR_CR33_OORTYP.
#define BM_DDR_CR33_OORTYP   (0x003F0000U) //!< Bit mask for DDR_CR33_OORTYP.
#define BS_DDR_CR33_OORTYP   (6U)          //!< Bit field size in bits for DDR_CR33_OORTYP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR33_OORTYP field.
#define BR_DDR_CR33_OORTYP   (HW_DDR_CR33.B.OORTYP)
#endif
//@}

/*!
 * @name Register DDR_CR33, field OORID[25:24] (RO)
 *
 * Source ID of the command that caused an out-of-range interrupt request.
 */
//@{
#define BP_DDR_CR33_OORID    (24U)         //!< Bit position for DDR_CR33_OORID.
#define BM_DDR_CR33_OORID    (0x03000000U) //!< Bit mask for DDR_CR33_OORID.
#define BS_DDR_CR33_OORID    (2U)          //!< Bit field size in bits for DDR_CR33_OORID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR33_OORID field.
#define BR_DDR_CR33_OORID    (HW_DDR_CR33.B.OORID)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR34 - DDR Control Register 34
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR34 - DDR Control Register 34 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr34
{
    uint32_t U;
    struct _hw_ddr_cr34_bitfields
    {
        uint32_t ODTRDC : 1;           //!< [0] ODT Read map CS
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t ODTWRCS : 1;          //!< [8] ODT Write map CS
        uint32_t RESERVED1 : 23;       //!< [31:9] Reserved
    } B;
} hw_ddr_cr34_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR34 register
 */
//@{
#define HW_DDR_CR34_ADDR         (REGS_DDR_BASE + 0x88U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR34              (*(__IO hw_ddr_cr34_t *) HW_DDR_CR34_ADDR)
#define HW_DDR_CR34_RD()         (HW_DDR_CR34.U)
#define HW_DDR_CR34_WR(v)        (HW_DDR_CR34.U = (v))
#define HW_DDR_CR34_SET(v)       (HW_DDR_CR34_WR(HW_DDR_CR34_RD() |  (v)))
#define HW_DDR_CR34_CLR(v)       (HW_DDR_CR34_WR(HW_DDR_CR34_RD() & ~(v)))
#define HW_DDR_CR34_TOG(v)       (HW_DDR_CR34_WR(HW_DDR_CR34_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR34 bitfields
 */

/*!
 * @name Register DDR_CR34, field ODTRDC[0] (RW)
 *
 * Determines if the chip select has termination when a read occurs on the chip
 * select . 0 Reserved ODT termination when CS performs a read 1 CS has active
 * ODT termination when CS performs a read
 */
//@{
#define BP_DDR_CR34_ODTRDC   (0U)          //!< Bit position for DDR_CR34_ODTRDC.
#define BM_DDR_CR34_ODTRDC   (0x00000001U) //!< Bit mask for DDR_CR34_ODTRDC.
#define BS_DDR_CR34_ODTRDC   (1U)          //!< Bit field size in bits for DDR_CR34_ODTRDC.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR34_ODTRDC field.
#define BR_DDR_CR34_ODTRDC   (BITBAND_ACCESS32(HW_DDR_CR34_ADDR, BP_DDR_CR34_ODTRDC))
#endif

//! @brief Format value for bitfield DDR_CR34_ODTRDC.
#define BF_DDR_CR34_ODTRDC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR34_ODTRDC), uint32_t) & BM_DDR_CR34_ODTRDC)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODTRDC field to a new value.
#define BW_DDR_CR34_ODTRDC(v) (BITBAND_ACCESS32(HW_DDR_CR34_ADDR, BP_DDR_CR34_ODTRDC) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR34, field ODTWRCS[8] (RW)
 *
 * Determines if the chip select has termination when a write occurs on the chip
 * select . 0 No ODT termination when CS performs a write 1 CS has active ODT
 * termination when CS performs a write
 */
//@{
#define BP_DDR_CR34_ODTWRCS  (8U)          //!< Bit position for DDR_CR34_ODTWRCS.
#define BM_DDR_CR34_ODTWRCS  (0x00000100U) //!< Bit mask for DDR_CR34_ODTWRCS.
#define BS_DDR_CR34_ODTWRCS  (1U)          //!< Bit field size in bits for DDR_CR34_ODTWRCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR34_ODTWRCS field.
#define BR_DDR_CR34_ODTWRCS  (BITBAND_ACCESS32(HW_DDR_CR34_ADDR, BP_DDR_CR34_ODTWRCS))
#endif

//! @brief Format value for bitfield DDR_CR34_ODTWRCS.
#define BF_DDR_CR34_ODTWRCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR34_ODTWRCS), uint32_t) & BM_DDR_CR34_ODTWRCS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODTWRCS field to a new value.
#define BW_DDR_CR34_ODTWRCS(v) (BITBAND_ACCESS32(HW_DDR_CR34_ADDR, BP_DDR_CR34_ODTWRCS) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR35 - DDR Control Register 35
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR35 - DDR Control Register 35 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr35
{
    uint32_t U;
    struct _hw_ddr_cr35_bitfields
    {
        uint32_t R2WSMCS : 4;          //!< [3:0] Read To Write Same Chip Select
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t W2RSMCS : 4;          //!< [11:8] Write To Read Same Chip Select
        uint32_t RESERVED1 : 20;       //!< [31:12] Reserved
    } B;
} hw_ddr_cr35_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR35 register
 */
//@{
#define HW_DDR_CR35_ADDR         (REGS_DDR_BASE + 0x8CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR35              (*(__I hw_ddr_cr35_t *) HW_DDR_CR35_ADDR)
#define HW_DDR_CR35_RD()         (HW_DDR_CR35.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR35 bitfields
 */

/*!
 * @name Register DDR_CR35, field R2WSMCS[3:0] (RO)
 *
 * Additional clocks of delay to insert between RD and WR transaction types to
 * chip select to meet ODT timing requirements.
 */
//@{
#define BP_DDR_CR35_R2WSMCS  (0U)          //!< Bit position for DDR_CR35_R2WSMCS.
#define BM_DDR_CR35_R2WSMCS  (0x0000000FU) //!< Bit mask for DDR_CR35_R2WSMCS.
#define BS_DDR_CR35_R2WSMCS  (4U)          //!< Bit field size in bits for DDR_CR35_R2WSMCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR35_R2WSMCS field.
#define BR_DDR_CR35_R2WSMCS  (HW_DDR_CR35.B.R2WSMCS)
#endif
//@}

/*!
 * @name Register DDR_CR35, field W2RSMCS[11:8] (RO)
 *
 * Additional clocks of delay to insert between WR and RD transaction types to
 * chip select to meet ODT timing requirements.
 */
//@{
#define BP_DDR_CR35_W2RSMCS  (8U)          //!< Bit position for DDR_CR35_W2RSMCS.
#define BM_DDR_CR35_W2RSMCS  (0x00000F00U) //!< Bit mask for DDR_CR35_W2RSMCS.
#define BS_DDR_CR35_W2RSMCS  (4U)          //!< Bit field size in bits for DDR_CR35_W2RSMCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR35_W2RSMCS field.
#define BR_DDR_CR35_W2RSMCS  (HW_DDR_CR35.B.W2RSMCS)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR36 - DDR Control Register 36
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR36 - DDR Control Register 36 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr36
{
    uint32_t U;
    struct _hw_ddr_cr36_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr36_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR36 register
 */
//@{
#define HW_DDR_CR36_ADDR         (REGS_DDR_BASE + 0x90U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR36              (*(__I hw_ddr_cr36_t *) HW_DDR_CR36_ADDR)
#define HW_DDR_CR36_RD()         (HW_DDR_CR36.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR36 bitfields
 */

/*!
 * @name Register DDR_CR36, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR36_Not_Used (0U)          //!< Bit position for DDR_CR36_Not_Used.
#define BM_DDR_CR36_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR36_Not_Used.
#define BS_DDR_CR36_Not_Used (16U)         //!< Bit field size in bits for DDR_CR36_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR36_Not_Used field.
#define BR_DDR_CR36_Not_Used (HW_DDR_CR36.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR36, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR36_NOT_USED (16U)         //!< Bit position for DDR_CR36_NOT_USED.
#define BM_DDR_CR36_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR36_NOT_USED.
#define BS_DDR_CR36_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR36_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR36_NOT_USED field.
#define BR_DDR_CR36_NOT_USED (HW_DDR_CR36.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR37 - DDR Control Register 37
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR37 - DDR Control Register 37 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr37
{
    uint32_t U;
    struct _hw_ddr_cr37_bitfields
    {
        uint32_t R2RSAME : 3;          //!< [2:0] R2R Same chip select delay
        uint32_t RESERVED0 : 5;        //!< [7:3] Reserved
        uint32_t R2WSAME : 3;          //!< [10:8] R2W Same chip select delay
        uint32_t RESERVED1 : 5;        //!< [15:11] Reserved
        uint32_t W2RSAME : 3;          //!< [18:16] W2R Same chip select delay
        uint32_t RESERVED2 : 5;        //!< [23:19] Reserved
        uint32_t W2WSAME : 3;          //!< [26:24] W2W Same chip select delay
        uint32_t RESERVED3 : 5;        //!< [31:27] Reserved
    } B;
} hw_ddr_cr37_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR37 register
 */
//@{
#define HW_DDR_CR37_ADDR         (REGS_DDR_BASE + 0x94U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR37              (*(__IO hw_ddr_cr37_t *) HW_DDR_CR37_ADDR)
#define HW_DDR_CR37_RD()         (HW_DDR_CR37.U)
#define HW_DDR_CR37_WR(v)        (HW_DDR_CR37.U = (v))
#define HW_DDR_CR37_SET(v)       (HW_DDR_CR37_WR(HW_DDR_CR37_RD() |  (v)))
#define HW_DDR_CR37_CLR(v)       (HW_DDR_CR37_WR(HW_DDR_CR37_RD() & ~(v)))
#define HW_DDR_CR37_TOG(v)       (HW_DDR_CR37_WR(HW_DDR_CR37_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR37 bitfields
 */

/*!
 * @name Register DDR_CR37, field R2RSAME[2:0] (RW)
 *
 * Additional clocks of delay to insert between reads and reads to the chip
 * select.
 */
//@{
#define BP_DDR_CR37_R2RSAME  (0U)          //!< Bit position for DDR_CR37_R2RSAME.
#define BM_DDR_CR37_R2RSAME  (0x00000007U) //!< Bit mask for DDR_CR37_R2RSAME.
#define BS_DDR_CR37_R2RSAME  (3U)          //!< Bit field size in bits for DDR_CR37_R2RSAME.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR37_R2RSAME field.
#define BR_DDR_CR37_R2RSAME  (HW_DDR_CR37.B.R2RSAME)
#endif

//! @brief Format value for bitfield DDR_CR37_R2RSAME.
#define BF_DDR_CR37_R2RSAME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR37_R2RSAME), uint32_t) & BM_DDR_CR37_R2RSAME)

#ifndef __LANGUAGE_ASM__
//! @brief Set the R2RSAME field to a new value.
#define BW_DDR_CR37_R2RSAME(v) (HW_DDR_CR37_WR((HW_DDR_CR37_RD() & ~BM_DDR_CR37_R2RSAME) | BF_DDR_CR37_R2RSAME(v)))
#endif
//@}

/*!
 * @name Register DDR_CR37, field R2WSAME[10:8] (RW)
 *
 * Additional clocks of delay to insert between reads and writes to the chip
 * select.
 */
//@{
#define BP_DDR_CR37_R2WSAME  (8U)          //!< Bit position for DDR_CR37_R2WSAME.
#define BM_DDR_CR37_R2WSAME  (0x00000700U) //!< Bit mask for DDR_CR37_R2WSAME.
#define BS_DDR_CR37_R2WSAME  (3U)          //!< Bit field size in bits for DDR_CR37_R2WSAME.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR37_R2WSAME field.
#define BR_DDR_CR37_R2WSAME  (HW_DDR_CR37.B.R2WSAME)
#endif

//! @brief Format value for bitfield DDR_CR37_R2WSAME.
#define BF_DDR_CR37_R2WSAME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR37_R2WSAME), uint32_t) & BM_DDR_CR37_R2WSAME)

#ifndef __LANGUAGE_ASM__
//! @brief Set the R2WSAME field to a new value.
#define BW_DDR_CR37_R2WSAME(v) (HW_DDR_CR37_WR((HW_DDR_CR37_RD() & ~BM_DDR_CR37_R2WSAME) | BF_DDR_CR37_R2WSAME(v)))
#endif
//@}

/*!
 * @name Register DDR_CR37, field W2RSAME[18:16] (RW)
 *
 * Additional clocks of delay to insert between writes and reads to the chip
 * select.
 */
//@{
#define BP_DDR_CR37_W2RSAME  (16U)         //!< Bit position for DDR_CR37_W2RSAME.
#define BM_DDR_CR37_W2RSAME  (0x00070000U) //!< Bit mask for DDR_CR37_W2RSAME.
#define BS_DDR_CR37_W2RSAME  (3U)          //!< Bit field size in bits for DDR_CR37_W2RSAME.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR37_W2RSAME field.
#define BR_DDR_CR37_W2RSAME  (HW_DDR_CR37.B.W2RSAME)
#endif

//! @brief Format value for bitfield DDR_CR37_W2RSAME.
#define BF_DDR_CR37_W2RSAME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR37_W2RSAME), uint32_t) & BM_DDR_CR37_W2RSAME)

#ifndef __LANGUAGE_ASM__
//! @brief Set the W2RSAME field to a new value.
#define BW_DDR_CR37_W2RSAME(v) (HW_DDR_CR37_WR((HW_DDR_CR37_RD() & ~BM_DDR_CR37_W2RSAME) | BF_DDR_CR37_W2RSAME(v)))
#endif
//@}

/*!
 * @name Register DDR_CR37, field W2WSAME[26:24] (RW)
 *
 * Additional clocks of delay to insert between writes and writes to the chip
 * select.
 */
//@{
#define BP_DDR_CR37_W2WSAME  (24U)         //!< Bit position for DDR_CR37_W2WSAME.
#define BM_DDR_CR37_W2WSAME  (0x07000000U) //!< Bit mask for DDR_CR37_W2WSAME.
#define BS_DDR_CR37_W2WSAME  (3U)          //!< Bit field size in bits for DDR_CR37_W2WSAME.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR37_W2WSAME field.
#define BR_DDR_CR37_W2WSAME  (HW_DDR_CR37.B.W2WSAME)
#endif

//! @brief Format value for bitfield DDR_CR37_W2WSAME.
#define BF_DDR_CR37_W2WSAME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR37_W2WSAME), uint32_t) & BM_DDR_CR37_W2WSAME)

#ifndef __LANGUAGE_ASM__
//! @brief Set the W2WSAME field to a new value.
#define BW_DDR_CR37_W2WSAME(v) (HW_DDR_CR37_WR((HW_DDR_CR37_RD() & ~BM_DDR_CR37_W2WSAME) | BF_DDR_CR37_W2WSAME(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR38 - DDR Control Register 38
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR38 - DDR Control Register 38 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr38
{
    uint32_t U;
    struct _hw_ddr_cr38_bitfields
    {
        uint32_t PDNCS : 5;            //!< [4:0] OCD Pull Down adjustment Chip Select
        uint32_t RESERVED0 : 3;        //!< [7:5] Reserved
        uint32_t PUPCS : 5;            //!< [12:8] OCD Pull Up adjustment Chip Select
        uint32_t RESERVED1 : 3;        //!< [15:13] Reserved
        uint32_t PWRCNT : 11;          //!< [26:16] Port 0 Write Count
        uint32_t RESERVED2 : 5;        //!< [31:27] Reserved
    } B;
} hw_ddr_cr38_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR38 register
 */
//@{
#define HW_DDR_CR38_ADDR         (REGS_DDR_BASE + 0x98U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR38              (*(__IO hw_ddr_cr38_t *) HW_DDR_CR38_ADDR)
#define HW_DDR_CR38_RD()         (HW_DDR_CR38.U)
#define HW_DDR_CR38_WR(v)        (HW_DDR_CR38.U = (v))
#define HW_DDR_CR38_SET(v)       (HW_DDR_CR38_WR(HW_DDR_CR38_RD() |  (v)))
#define HW_DDR_CR38_CLR(v)       (HW_DDR_CR38_WR(HW_DDR_CR38_RD() & ~(v)))
#define HW_DDR_CR38_TOG(v)       (HW_DDR_CR38_WR(HW_DDR_CR38_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR38 bitfields
 */

/*!
 * @name Register DDR_CR38, field PDNCS[4:0] (RW)
 *
 * Off-chip driver (OCD) pull-down adjustment setting for DRAMs for the chip
 * select . The memory controller issues OCD adjustment commands during power-up.
 * Bit[4] 0 Decrement OCD settings 1 Increment OCD settings Bit[3:0] Number of OCD
 * adjustment commands to issue
 */
//@{
#define BP_DDR_CR38_PDNCS    (0U)          //!< Bit position for DDR_CR38_PDNCS.
#define BM_DDR_CR38_PDNCS    (0x0000001FU) //!< Bit mask for DDR_CR38_PDNCS.
#define BS_DDR_CR38_PDNCS    (5U)          //!< Bit field size in bits for DDR_CR38_PDNCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR38_PDNCS field.
#define BR_DDR_CR38_PDNCS    (HW_DDR_CR38.B.PDNCS)
#endif

//! @brief Format value for bitfield DDR_CR38_PDNCS.
#define BF_DDR_CR38_PDNCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR38_PDNCS), uint32_t) & BM_DDR_CR38_PDNCS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PDNCS field to a new value.
#define BW_DDR_CR38_PDNCS(v) (HW_DDR_CR38_WR((HW_DDR_CR38_RD() & ~BM_DDR_CR38_PDNCS) | BF_DDR_CR38_PDNCS(v)))
#endif
//@}

/*!
 * @name Register DDR_CR38, field PUPCS[12:8] (RW)
 *
 * Off-chip driver (OCD) pull-up adjustment setting for DRAMs for the chip
 * select . The memory controller issues OCD adjustment commands during power-up.
 * Bit[12] 0 Decrement OCD settings 1 Increment OCD settings Bit[11:8] Number of OCD
 * adjustment commands to issue
 */
//@{
#define BP_DDR_CR38_PUPCS    (8U)          //!< Bit position for DDR_CR38_PUPCS.
#define BM_DDR_CR38_PUPCS    (0x00001F00U) //!< Bit mask for DDR_CR38_PUPCS.
#define BS_DDR_CR38_PUPCS    (5U)          //!< Bit field size in bits for DDR_CR38_PUPCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR38_PUPCS field.
#define BR_DDR_CR38_PUPCS    (HW_DDR_CR38.B.PUPCS)
#endif

//! @brief Format value for bitfield DDR_CR38_PUPCS.
#define BF_DDR_CR38_PUPCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR38_PUPCS), uint32_t) & BM_DDR_CR38_PUPCS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PUPCS field to a new value.
#define BW_DDR_CR38_PUPCS(v) (HW_DDR_CR38_WR((HW_DDR_CR38_RD() & ~BM_DDR_CR38_PUPCS) | BF_DDR_CR38_PUPCS(v)))
#endif
//@}

/*!
 * @name Register DDR_CR38, field PWRCNT[26:16] (RW)
 *
 * Number of bytes for INCR write command on port 0. The logic subdivides an
 * INCR request into memory controller core commands of the size of this parameter.
 * The logic continues sending bursts of this size as the previous request is
 * transmitted by the port. If the INCR command is terminated on an unnatural
 * boundary, the logic discards the unnecessary words. The value defined in this
 * parameter must be a multiple of four . Clearing this parameter causes the port to
 * issue commands of zero length to the memory controller core, which the core
 * interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR38_PWRCNT   (16U)         //!< Bit position for DDR_CR38_PWRCNT.
#define BM_DDR_CR38_PWRCNT   (0x07FF0000U) //!< Bit mask for DDR_CR38_PWRCNT.
#define BS_DDR_CR38_PWRCNT   (11U)         //!< Bit field size in bits for DDR_CR38_PWRCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR38_PWRCNT field.
#define BR_DDR_CR38_PWRCNT   (HW_DDR_CR38.B.PWRCNT)
#endif

//! @brief Format value for bitfield DDR_CR38_PWRCNT.
#define BF_DDR_CR38_PWRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR38_PWRCNT), uint32_t) & BM_DDR_CR38_PWRCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PWRCNT field to a new value.
#define BW_DDR_CR38_PWRCNT(v) (HW_DDR_CR38_WR((HW_DDR_CR38_RD() & ~BM_DDR_CR38_PWRCNT) | BF_DDR_CR38_PWRCNT(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR39 - DDR Control Register 39
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR39 - DDR Control Register 39 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr39
{
    uint32_t U;
    struct _hw_ddr_cr39_bitfields
    {
        uint32_t P0RDCNT : 11;         //!< [10:0] Port 0 Read command Count
        uint32_t RESERVED0 : 5;        //!< [15:11] Reserved
        uint32_t RP0 : 2;              //!< [17:16] Port 0 Read command Priority
        uint32_t RESERVED1 : 6;        //!< [23:18] Reserved
        uint32_t WP0 : 2;              //!< [25:24] Port 0 Write command Priority
        uint32_t RESERVED2 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_cr39_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR39 register
 */
//@{
#define HW_DDR_CR39_ADDR         (REGS_DDR_BASE + 0x9CU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR39              (*(__IO hw_ddr_cr39_t *) HW_DDR_CR39_ADDR)
#define HW_DDR_CR39_RD()         (HW_DDR_CR39.U)
#define HW_DDR_CR39_WR(v)        (HW_DDR_CR39.U = (v))
#define HW_DDR_CR39_SET(v)       (HW_DDR_CR39_WR(HW_DDR_CR39_RD() |  (v)))
#define HW_DDR_CR39_CLR(v)       (HW_DDR_CR39_WR(HW_DDR_CR39_RD() & ~(v)))
#define HW_DDR_CR39_TOG(v)       (HW_DDR_CR39_WR(HW_DDR_CR39_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR39 bitfields
 */

/*!
 * @name Register DDR_CR39, field P0RDCNT[10:0] (RW)
 *
 * Number of bytes for INCR read command on port 0. The logic subdivides an INCR
 * request into memory controller core commands of the size of this parameter.
 * The logic continues requesting bursts of this size as soon as the previous
 * request is received by the crossbar port. If the INCR command is terminated on an
 * unnatural boundary, the logic discards the unnecessary words. The value
 * defined in this parameter must be a multiple of four . Clearing this parameter
 * causes the port to issue commands of zero length to the memory controller core,
 * which the core interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR39_P0RDCNT  (0U)          //!< Bit position for DDR_CR39_P0RDCNT.
#define BM_DDR_CR39_P0RDCNT  (0x000007FFU) //!< Bit mask for DDR_CR39_P0RDCNT.
#define BS_DDR_CR39_P0RDCNT  (11U)         //!< Bit field size in bits for DDR_CR39_P0RDCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR39_P0RDCNT field.
#define BR_DDR_CR39_P0RDCNT  (HW_DDR_CR39.B.P0RDCNT)
#endif

//! @brief Format value for bitfield DDR_CR39_P0RDCNT.
#define BF_DDR_CR39_P0RDCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR39_P0RDCNT), uint32_t) & BM_DDR_CR39_P0RDCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0RDCNT field to a new value.
#define BW_DDR_CR39_P0RDCNT(v) (HW_DDR_CR39_WR((HW_DDR_CR39_RD() & ~BM_DDR_CR39_P0RDCNT) | BF_DDR_CR39_P0RDCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR39, field RP0[17:16] (RW)
 *
 * Sets port 0 read command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR39_RP0      (16U)         //!< Bit position for DDR_CR39_RP0.
#define BM_DDR_CR39_RP0      (0x00030000U) //!< Bit mask for DDR_CR39_RP0.
#define BS_DDR_CR39_RP0      (2U)          //!< Bit field size in bits for DDR_CR39_RP0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR39_RP0 field.
#define BR_DDR_CR39_RP0      (HW_DDR_CR39.B.RP0)
#endif

//! @brief Format value for bitfield DDR_CR39_RP0.
#define BF_DDR_CR39_RP0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR39_RP0), uint32_t) & BM_DDR_CR39_RP0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RP0 field to a new value.
#define BW_DDR_CR39_RP0(v)   (HW_DDR_CR39_WR((HW_DDR_CR39_RD() & ~BM_DDR_CR39_RP0) | BF_DDR_CR39_RP0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR39, field WP0[25:24] (RW)
 *
 * Sets port 0 write command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR39_WP0      (24U)         //!< Bit position for DDR_CR39_WP0.
#define BM_DDR_CR39_WP0      (0x03000000U) //!< Bit mask for DDR_CR39_WP0.
#define BS_DDR_CR39_WP0      (2U)          //!< Bit field size in bits for DDR_CR39_WP0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR39_WP0 field.
#define BR_DDR_CR39_WP0      (HW_DDR_CR39.B.WP0)
#endif

//! @brief Format value for bitfield DDR_CR39_WP0.
#define BF_DDR_CR39_WP0(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR39_WP0), uint32_t) & BM_DDR_CR39_WP0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WP0 field to a new value.
#define BW_DDR_CR39_WP0(v)   (HW_DDR_CR39_WR((HW_DDR_CR39_RD() & ~BM_DDR_CR39_WP0) | BF_DDR_CR39_WP0(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR40 - DDR Control Register 40
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR40 - DDR Control Register 40 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr40
{
    uint32_t U;
    struct _hw_ddr_cr40_bitfields
    {
        uint32_t P0TYP : 2;            //!< [1:0] Port 0 Type
        uint32_t RESERVED0 : 6;        //!< [7:2] Reserved
        uint32_t P1WRCNT : 11;         //!< [18:8] Port 1 Write command Count
        uint32_t RESERVED1 : 13;       //!< [31:19] Reserved
    } B;
} hw_ddr_cr40_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR40 register
 */
//@{
#define HW_DDR_CR40_ADDR         (REGS_DDR_BASE + 0xA0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR40              (*(__IO hw_ddr_cr40_t *) HW_DDR_CR40_ADDR)
#define HW_DDR_CR40_RD()         (HW_DDR_CR40.U)
#define HW_DDR_CR40_WR(v)        (HW_DDR_CR40.U = (v))
#define HW_DDR_CR40_SET(v)       (HW_DDR_CR40_WR(HW_DDR_CR40_RD() |  (v)))
#define HW_DDR_CR40_CLR(v)       (HW_DDR_CR40_WR(HW_DDR_CR40_RD() & ~(v)))
#define HW_DDR_CR40_TOG(v)       (HW_DDR_CR40_WR(HW_DDR_CR40_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR40 bitfields
 */

/*!
 * @name Register DDR_CR40, field P0TYP[1:0] (RW)
 *
 * Clock domain relativity between port 0 and the controller core. 00
 * Asynchronous 01 Reserved 01 Reserved 11 Synchronous
 */
//@{
#define BP_DDR_CR40_P0TYP    (0U)          //!< Bit position for DDR_CR40_P0TYP.
#define BM_DDR_CR40_P0TYP    (0x00000003U) //!< Bit mask for DDR_CR40_P0TYP.
#define BS_DDR_CR40_P0TYP    (2U)          //!< Bit field size in bits for DDR_CR40_P0TYP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR40_P0TYP field.
#define BR_DDR_CR40_P0TYP    (HW_DDR_CR40.B.P0TYP)
#endif

//! @brief Format value for bitfield DDR_CR40_P0TYP.
#define BF_DDR_CR40_P0TYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR40_P0TYP), uint32_t) & BM_DDR_CR40_P0TYP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0TYP field to a new value.
#define BW_DDR_CR40_P0TYP(v) (HW_DDR_CR40_WR((HW_DDR_CR40_RD() & ~BM_DDR_CR40_P0TYP) | BF_DDR_CR40_P0TYP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR40, field P1WRCNT[18:8] (RW)
 *
 * Number of bytes for INCR write command on port 1. The logic subdivides an
 * INCR request into memory controller core commands of the size of this parameter.
 * The logic continues sending bursts of this size as the previous request is
 * transmitted by the crossbar port. If the INCR command is terminated on an
 * unnatural boundary, the logic discards the unnecessary words. The value defined in
 * this parameter must be a multiple of four . Clearing this parameter causes the
 * port to issue commands of zero length to the memory controller core, which the
 * core interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR40_P1WRCNT  (8U)          //!< Bit position for DDR_CR40_P1WRCNT.
#define BM_DDR_CR40_P1WRCNT  (0x0007FF00U) //!< Bit mask for DDR_CR40_P1WRCNT.
#define BS_DDR_CR40_P1WRCNT  (11U)         //!< Bit field size in bits for DDR_CR40_P1WRCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR40_P1WRCNT field.
#define BR_DDR_CR40_P1WRCNT  (HW_DDR_CR40.B.P1WRCNT)
#endif

//! @brief Format value for bitfield DDR_CR40_P1WRCNT.
#define BF_DDR_CR40_P1WRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR40_P1WRCNT), uint32_t) & BM_DDR_CR40_P1WRCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1WRCNT field to a new value.
#define BW_DDR_CR40_P1WRCNT(v) (HW_DDR_CR40_WR((HW_DDR_CR40_RD() & ~BM_DDR_CR40_P1WRCNT) | BF_DDR_CR40_P1WRCNT(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR41 - DDR Control Register 41
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR41 - DDR Control Register 41 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr41
{
    uint32_t U;
    struct _hw_ddr_cr41_bitfields
    {
        uint32_t P1RDCNT : 11;         //!< [10:0] Port 1 Read command Count
        uint32_t RESERVED0 : 5;        //!< [15:11] Reserved
        uint32_t RP1 : 2;              //!< [17:16] Read command priority Port 1
        uint32_t RESERVED1 : 6;        //!< [23:18] Reserved
        uint32_t WP1 : 2;              //!< [25:24] Write command priority Port 1
        uint32_t RESERVED2 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_cr41_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR41 register
 */
//@{
#define HW_DDR_CR41_ADDR         (REGS_DDR_BASE + 0xA4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR41              (*(__IO hw_ddr_cr41_t *) HW_DDR_CR41_ADDR)
#define HW_DDR_CR41_RD()         (HW_DDR_CR41.U)
#define HW_DDR_CR41_WR(v)        (HW_DDR_CR41.U = (v))
#define HW_DDR_CR41_SET(v)       (HW_DDR_CR41_WR(HW_DDR_CR41_RD() |  (v)))
#define HW_DDR_CR41_CLR(v)       (HW_DDR_CR41_WR(HW_DDR_CR41_RD() & ~(v)))
#define HW_DDR_CR41_TOG(v)       (HW_DDR_CR41_WR(HW_DDR_CR41_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR41 bitfields
 */

/*!
 * @name Register DDR_CR41, field P1RDCNT[10:0] (RW)
 *
 * Number of bytes for INCR read command on port 1. The logic subdivides an INCR
 * request into memory controller core commands of the size of this parameter.
 * The logic continues requesting bursts of this size as soon as the previous
 * request is received by the crossbar port. If the INCR command is terminated on an
 * unnatural boundary, the logic discards the unnecessary words. The value
 * defined in this parameter must be a multiple of four . Clearing this parameter
 * causes the port to issue commands of zero length to the controller core, which the
 * core interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR41_P1RDCNT  (0U)          //!< Bit position for DDR_CR41_P1RDCNT.
#define BM_DDR_CR41_P1RDCNT  (0x000007FFU) //!< Bit mask for DDR_CR41_P1RDCNT.
#define BS_DDR_CR41_P1RDCNT  (11U)         //!< Bit field size in bits for DDR_CR41_P1RDCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR41_P1RDCNT field.
#define BR_DDR_CR41_P1RDCNT  (HW_DDR_CR41.B.P1RDCNT)
#endif

//! @brief Format value for bitfield DDR_CR41_P1RDCNT.
#define BF_DDR_CR41_P1RDCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR41_P1RDCNT), uint32_t) & BM_DDR_CR41_P1RDCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1RDCNT field to a new value.
#define BW_DDR_CR41_P1RDCNT(v) (HW_DDR_CR41_WR((HW_DDR_CR41_RD() & ~BM_DDR_CR41_P1RDCNT) | BF_DDR_CR41_P1RDCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR41, field RP1[17:16] (RW)
 *
 * Sets the port 1 read command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR41_RP1      (16U)         //!< Bit position for DDR_CR41_RP1.
#define BM_DDR_CR41_RP1      (0x00030000U) //!< Bit mask for DDR_CR41_RP1.
#define BS_DDR_CR41_RP1      (2U)          //!< Bit field size in bits for DDR_CR41_RP1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR41_RP1 field.
#define BR_DDR_CR41_RP1      (HW_DDR_CR41.B.RP1)
#endif

//! @brief Format value for bitfield DDR_CR41_RP1.
#define BF_DDR_CR41_RP1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR41_RP1), uint32_t) & BM_DDR_CR41_RP1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RP1 field to a new value.
#define BW_DDR_CR41_RP1(v)   (HW_DDR_CR41_WR((HW_DDR_CR41_RD() & ~BM_DDR_CR41_RP1) | BF_DDR_CR41_RP1(v)))
#endif
//@}

/*!
 * @name Register DDR_CR41, field WP1[25:24] (RW)
 *
 * Sets the port 1 write command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR41_WP1      (24U)         //!< Bit position for DDR_CR41_WP1.
#define BM_DDR_CR41_WP1      (0x03000000U) //!< Bit mask for DDR_CR41_WP1.
#define BS_DDR_CR41_WP1      (2U)          //!< Bit field size in bits for DDR_CR41_WP1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR41_WP1 field.
#define BR_DDR_CR41_WP1      (HW_DDR_CR41.B.WP1)
#endif

//! @brief Format value for bitfield DDR_CR41_WP1.
#define BF_DDR_CR41_WP1(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR41_WP1), uint32_t) & BM_DDR_CR41_WP1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WP1 field to a new value.
#define BW_DDR_CR41_WP1(v)   (HW_DDR_CR41_WR((HW_DDR_CR41_RD() & ~BM_DDR_CR41_WP1) | BF_DDR_CR41_WP1(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR42 - DDR Control Register 42
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR42 - DDR Control Register 42 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr42
{
    uint32_t U;
    struct _hw_ddr_cr42_bitfields
    {
        uint32_t P1TYP : 2;            //!< [1:0] Port 1 Type
        uint32_t RESERVED0 : 6;        //!< [7:2] Reserved
        uint32_t P2WRCNT : 11;         //!< [18:8] Port 2 Write command Count
        uint32_t RESERVED1 : 13;       //!< [31:19] Reserved
    } B;
} hw_ddr_cr42_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR42 register
 */
//@{
#define HW_DDR_CR42_ADDR         (REGS_DDR_BASE + 0xA8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR42              (*(__IO hw_ddr_cr42_t *) HW_DDR_CR42_ADDR)
#define HW_DDR_CR42_RD()         (HW_DDR_CR42.U)
#define HW_DDR_CR42_WR(v)        (HW_DDR_CR42.U = (v))
#define HW_DDR_CR42_SET(v)       (HW_DDR_CR42_WR(HW_DDR_CR42_RD() |  (v)))
#define HW_DDR_CR42_CLR(v)       (HW_DDR_CR42_WR(HW_DDR_CR42_RD() & ~(v)))
#define HW_DDR_CR42_TOG(v)       (HW_DDR_CR42_WR(HW_DDR_CR42_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR42 bitfields
 */

/*!
 * @name Register DDR_CR42, field P1TYP[1:0] (RW)
 *
 * Clock domain relativity between port 1 and the controller core. 00
 * Asynchronous 01 Reserved 01 Reserved 11 Synchronous
 */
//@{
#define BP_DDR_CR42_P1TYP    (0U)          //!< Bit position for DDR_CR42_P1TYP.
#define BM_DDR_CR42_P1TYP    (0x00000003U) //!< Bit mask for DDR_CR42_P1TYP.
#define BS_DDR_CR42_P1TYP    (2U)          //!< Bit field size in bits for DDR_CR42_P1TYP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR42_P1TYP field.
#define BR_DDR_CR42_P1TYP    (HW_DDR_CR42.B.P1TYP)
#endif

//! @brief Format value for bitfield DDR_CR42_P1TYP.
#define BF_DDR_CR42_P1TYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR42_P1TYP), uint32_t) & BM_DDR_CR42_P1TYP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1TYP field to a new value.
#define BW_DDR_CR42_P1TYP(v) (HW_DDR_CR42_WR((HW_DDR_CR42_RD() & ~BM_DDR_CR42_P1TYP) | BF_DDR_CR42_P1TYP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR42, field P2WRCNT[18:8] (RW)
 *
 * Number of bytes for INCR write command on port 2. The logic subdivides an
 * INCR request into memory controller core commands of the size of this parameter.
 * The logic continues sending bursts of this size as the previous request is
 * transmitted by the crossbar port. If the INCR command is terminated on an
 * unnatural boundary, the logic discards the unnecessary words. The value defined in
 * this parameter must be a multiple of four . Clearing this parameter causes the
 * port to issue commands of zero length to the memory controller core, which the
 * core interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR42_P2WRCNT  (8U)          //!< Bit position for DDR_CR42_P2WRCNT.
#define BM_DDR_CR42_P2WRCNT  (0x0007FF00U) //!< Bit mask for DDR_CR42_P2WRCNT.
#define BS_DDR_CR42_P2WRCNT  (11U)         //!< Bit field size in bits for DDR_CR42_P2WRCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR42_P2WRCNT field.
#define BR_DDR_CR42_P2WRCNT  (HW_DDR_CR42.B.P2WRCNT)
#endif

//! @brief Format value for bitfield DDR_CR42_P2WRCNT.
#define BF_DDR_CR42_P2WRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR42_P2WRCNT), uint32_t) & BM_DDR_CR42_P2WRCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2WRCNT field to a new value.
#define BW_DDR_CR42_P2WRCNT(v) (HW_DDR_CR42_WR((HW_DDR_CR42_RD() & ~BM_DDR_CR42_P2WRCNT) | BF_DDR_CR42_P2WRCNT(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR43 - DDR Control Register 43
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR43 - DDR Control Register 43 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr43
{
    uint32_t U;
    struct _hw_ddr_cr43_bitfields
    {
        uint32_t P2RDCNT : 11;         //!< [10:0] Port 2 Read command Count
        uint32_t RESERVED0 : 5;        //!< [15:11] Reserved
        uint32_t RP2 : 2;              //!< [17:16] Read command priority Port 2
        uint32_t RESERVED1 : 6;        //!< [23:18] Reserved
        uint32_t WP2 : 2;              //!< [25:24] Write command priority Port 2
        uint32_t RESERVED2 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_cr43_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR43 register
 */
//@{
#define HW_DDR_CR43_ADDR         (REGS_DDR_BASE + 0xACU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR43              (*(__IO hw_ddr_cr43_t *) HW_DDR_CR43_ADDR)
#define HW_DDR_CR43_RD()         (HW_DDR_CR43.U)
#define HW_DDR_CR43_WR(v)        (HW_DDR_CR43.U = (v))
#define HW_DDR_CR43_SET(v)       (HW_DDR_CR43_WR(HW_DDR_CR43_RD() |  (v)))
#define HW_DDR_CR43_CLR(v)       (HW_DDR_CR43_WR(HW_DDR_CR43_RD() & ~(v)))
#define HW_DDR_CR43_TOG(v)       (HW_DDR_CR43_WR(HW_DDR_CR43_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR43 bitfields
 */

/*!
 * @name Register DDR_CR43, field P2RDCNT[10:0] (RW)
 *
 * Number of bytes for INCR read command on port 2. The logic subdivides an INCR
 * request into memory controller core commands of the size of this parameter.
 * The logic continues requesting bursts of this size as soon as the previous
 * request is received by the crossbar port. If the INCR command is terminated on an
 * unnatural boundary, the logic discards the unnecessary words. The value
 * defined in this parameter must be a multiple of four . Clearing this parameter
 * causes the port to issue commands of zero length to the controller core, which the
 * core interprets as the pre-configured value of 128 bytes.
 */
//@{
#define BP_DDR_CR43_P2RDCNT  (0U)          //!< Bit position for DDR_CR43_P2RDCNT.
#define BM_DDR_CR43_P2RDCNT  (0x000007FFU) //!< Bit mask for DDR_CR43_P2RDCNT.
#define BS_DDR_CR43_P2RDCNT  (11U)         //!< Bit field size in bits for DDR_CR43_P2RDCNT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR43_P2RDCNT field.
#define BR_DDR_CR43_P2RDCNT  (HW_DDR_CR43.B.P2RDCNT)
#endif

//! @brief Format value for bitfield DDR_CR43_P2RDCNT.
#define BF_DDR_CR43_P2RDCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR43_P2RDCNT), uint32_t) & BM_DDR_CR43_P2RDCNT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2RDCNT field to a new value.
#define BW_DDR_CR43_P2RDCNT(v) (HW_DDR_CR43_WR((HW_DDR_CR43_RD() & ~BM_DDR_CR43_P2RDCNT) | BF_DDR_CR43_P2RDCNT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR43, field RP2[17:16] (RW)
 *
 * Sets the port 2 read command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR43_RP2      (16U)         //!< Bit position for DDR_CR43_RP2.
#define BM_DDR_CR43_RP2      (0x00030000U) //!< Bit mask for DDR_CR43_RP2.
#define BS_DDR_CR43_RP2      (2U)          //!< Bit field size in bits for DDR_CR43_RP2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR43_RP2 field.
#define BR_DDR_CR43_RP2      (HW_DDR_CR43.B.RP2)
#endif

//! @brief Format value for bitfield DDR_CR43_RP2.
#define BF_DDR_CR43_RP2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR43_RP2), uint32_t) & BM_DDR_CR43_RP2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RP2 field to a new value.
#define BW_DDR_CR43_RP2(v)   (HW_DDR_CR43_WR((HW_DDR_CR43_RD() & ~BM_DDR_CR43_RP2) | BF_DDR_CR43_RP2(v)))
#endif
//@}

/*!
 * @name Register DDR_CR43, field WP2[25:24] (RW)
 *
 * Sets the port 2 write command priority.
 *
 * Values:
 * - 00 - Highest
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest
 */
//@{
#define BP_DDR_CR43_WP2      (24U)         //!< Bit position for DDR_CR43_WP2.
#define BM_DDR_CR43_WP2      (0x03000000U) //!< Bit mask for DDR_CR43_WP2.
#define BS_DDR_CR43_WP2      (2U)          //!< Bit field size in bits for DDR_CR43_WP2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR43_WP2 field.
#define BR_DDR_CR43_WP2      (HW_DDR_CR43.B.WP2)
#endif

//! @brief Format value for bitfield DDR_CR43_WP2.
#define BF_DDR_CR43_WP2(v)   (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR43_WP2), uint32_t) & BM_DDR_CR43_WP2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WP2 field to a new value.
#define BW_DDR_CR43_WP2(v)   (HW_DDR_CR43_WR((HW_DDR_CR43_RD() & ~BM_DDR_CR43_WP2) | BF_DDR_CR43_WP2(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR44 - DDR Control Register 44
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR44 - DDR Control Register 44 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr44
{
    uint32_t U;
    struct _hw_ddr_cr44_bitfields
    {
        uint32_t P2TYP : 2;            //!< [1:0] Port 2 Type
        uint32_t RESERVED0 : 6;        //!< [7:2] Reserved
        uint32_t WRRLAT : 1;           //!< [8] WRR Latency
        uint32_t RESERVED1 : 7;        //!< [15:9] Reserved
        uint32_t WRRSHARE : 1;         //!< [16] WRR Shared arbitration
        uint32_t RESERVED2 : 7;        //!< [23:17] Reserved
        uint32_t WRRERR : 4;           //!< [27:24] WRR parameters Error
        uint32_t RESERVED3 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr44_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR44 register
 */
//@{
#define HW_DDR_CR44_ADDR         (REGS_DDR_BASE + 0xB0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR44              (*(__IO hw_ddr_cr44_t *) HW_DDR_CR44_ADDR)
#define HW_DDR_CR44_RD()         (HW_DDR_CR44.U)
#define HW_DDR_CR44_WR(v)        (HW_DDR_CR44.U = (v))
#define HW_DDR_CR44_SET(v)       (HW_DDR_CR44_WR(HW_DDR_CR44_RD() |  (v)))
#define HW_DDR_CR44_CLR(v)       (HW_DDR_CR44_WR(HW_DDR_CR44_RD() & ~(v)))
#define HW_DDR_CR44_TOG(v)       (HW_DDR_CR44_WR(HW_DDR_CR44_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR44 bitfields
 */

/*!
 * @name Register DDR_CR44, field P2TYP[1:0] (RW)
 *
 * Clock domain relativity between port 2 and the controller core. 00
 * Asynchronous 01 Reserved 01 Reserved 11 Synchronous
 */
//@{
#define BP_DDR_CR44_P2TYP    (0U)          //!< Bit position for DDR_CR44_P2TYP.
#define BM_DDR_CR44_P2TYP    (0x00000003U) //!< Bit mask for DDR_CR44_P2TYP.
#define BS_DDR_CR44_P2TYP    (2U)          //!< Bit field size in bits for DDR_CR44_P2TYP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR44_P2TYP field.
#define BR_DDR_CR44_P2TYP    (HW_DDR_CR44.B.P2TYP)
#endif

//! @brief Format value for bitfield DDR_CR44_P2TYP.
#define BF_DDR_CR44_P2TYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR44_P2TYP), uint32_t) & BM_DDR_CR44_P2TYP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2TYP field to a new value.
#define BW_DDR_CR44_P2TYP(v) (HW_DDR_CR44_WR((HW_DDR_CR44_RD() & ~BM_DDR_CR44_P2TYP) | BF_DDR_CR44_P2TYP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR44, field WRRLAT[8] (RW)
 *
 * Free-running or limited weighted-round-robin (WRR) latency control.
 *
 * Values:
 * - 0 - Free-running
 * - 1 - Limited
 */
//@{
#define BP_DDR_CR44_WRRLAT   (8U)          //!< Bit position for DDR_CR44_WRRLAT.
#define BM_DDR_CR44_WRRLAT   (0x00000100U) //!< Bit mask for DDR_CR44_WRRLAT.
#define BS_DDR_CR44_WRRLAT   (1U)          //!< Bit field size in bits for DDR_CR44_WRRLAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR44_WRRLAT field.
#define BR_DDR_CR44_WRRLAT   (BITBAND_ACCESS32(HW_DDR_CR44_ADDR, BP_DDR_CR44_WRRLAT))
#endif

//! @brief Format value for bitfield DDR_CR44_WRRLAT.
#define BF_DDR_CR44_WRRLAT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR44_WRRLAT), uint32_t) & BM_DDR_CR44_WRRLAT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRRLAT field to a new value.
#define BW_DDR_CR44_WRRLAT(v) (BITBAND_ACCESS32(HW_DDR_CR44_ADDR, BP_DDR_CR44_WRRLAT) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR44, field WRRSHARE[16] (RW)
 *
 * Per-port pair shared arbitration for weighted-round-robin (WRR). Port 2 is
 * treated independently from port 0 or port 1 for arbitration.
 *
 * Values:
 * - 0 - Port 0 and port 1 are treated independently for arbitration
 * - 1 - Port 0 and port 1 are grouped together for arbitration
 */
//@{
#define BP_DDR_CR44_WRRSHARE (16U)         //!< Bit position for DDR_CR44_WRRSHARE.
#define BM_DDR_CR44_WRRSHARE (0x00010000U) //!< Bit mask for DDR_CR44_WRRSHARE.
#define BS_DDR_CR44_WRRSHARE (1U)          //!< Bit field size in bits for DDR_CR44_WRRSHARE.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR44_WRRSHARE field.
#define BR_DDR_CR44_WRRSHARE (BITBAND_ACCESS32(HW_DDR_CR44_ADDR, BP_DDR_CR44_WRRSHARE))
#endif

//! @brief Format value for bitfield DDR_CR44_WRRSHARE.
#define BF_DDR_CR44_WRRSHARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR44_WRRSHARE), uint32_t) & BM_DDR_CR44_WRRSHARE)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRRSHARE field to a new value.
#define BW_DDR_CR44_WRRSHARE(v) (BITBAND_ACCESS32(HW_DDR_CR44_ADDR, BP_DDR_CR44_WRRSHARE) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR44, field WRRERR[27:24] (RO)
 *
 * Error/warnings related to weighted-round-robin (WRR) parameters. Bit[27]: The
 * port ordering parameter values for paired ports is not sequential. Bit[26]:
 * The relative priority values for any of the ports paired through the
 * weighted_round_robin_weight_sharing parameter are not identical. Bit[25]: Any of the
 * relative priority parameters have been programmed with a zero value. Bit[24] The
 * port ordering parameters do not all contain unique values.
 */
//@{
#define BP_DDR_CR44_WRRERR   (24U)         //!< Bit position for DDR_CR44_WRRERR.
#define BM_DDR_CR44_WRRERR   (0x0F000000U) //!< Bit mask for DDR_CR44_WRRERR.
#define BS_DDR_CR44_WRRERR   (4U)          //!< Bit field size in bits for DDR_CR44_WRRERR.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR44_WRRERR field.
#define BR_DDR_CR44_WRRERR   (HW_DDR_CR44.B.WRRERR)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR45 - DDR Control Register 45
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR45 - DDR Control Register 45 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr45
{
    uint32_t U;
    struct _hw_ddr_cr45_bitfields
    {
        uint32_t P0PRI0 : 4;           //!< [3:0] Port 0 Priority 0 commands
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t P0PRI1 : 4;           //!< [11:8] Port 0 Priority 1 commands
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t P0PRI2 : 4;           //!< [19:16] Port 0 Priority 2 commands
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t P0PRI3 : 4;           //!< [27:24] Port 0 Priority 3 commands
        uint32_t RESERVED3 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr45_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR45 register
 */
//@{
#define HW_DDR_CR45_ADDR         (REGS_DDR_BASE + 0xB4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR45              (*(__IO hw_ddr_cr45_t *) HW_DDR_CR45_ADDR)
#define HW_DDR_CR45_RD()         (HW_DDR_CR45.U)
#define HW_DDR_CR45_WR(v)        (HW_DDR_CR45.U = (v))
#define HW_DDR_CR45_SET(v)       (HW_DDR_CR45_WR(HW_DDR_CR45_RD() |  (v)))
#define HW_DDR_CR45_CLR(v)       (HW_DDR_CR45_WR(HW_DDR_CR45_RD() & ~(v)))
#define HW_DDR_CR45_TOG(v)       (HW_DDR_CR45_WR(HW_DDR_CR45_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR45 bitfields
 */

/*!
 * @name Register DDR_CR45, field P0PRI0[3:0] (RW)
 *
 * Relative priority of priority 0 commands from port 0.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR45_P0PRI0   (0U)          //!< Bit position for DDR_CR45_P0PRI0.
#define BM_DDR_CR45_P0PRI0   (0x0000000FU) //!< Bit mask for DDR_CR45_P0PRI0.
#define BS_DDR_CR45_P0PRI0   (4U)          //!< Bit field size in bits for DDR_CR45_P0PRI0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR45_P0PRI0 field.
#define BR_DDR_CR45_P0PRI0   (HW_DDR_CR45.B.P0PRI0)
#endif

//! @brief Format value for bitfield DDR_CR45_P0PRI0.
#define BF_DDR_CR45_P0PRI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR45_P0PRI0), uint32_t) & BM_DDR_CR45_P0PRI0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0PRI0 field to a new value.
#define BW_DDR_CR45_P0PRI0(v) (HW_DDR_CR45_WR((HW_DDR_CR45_RD() & ~BM_DDR_CR45_P0PRI0) | BF_DDR_CR45_P0PRI0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR45, field P0PRI1[11:8] (RW)
 *
 * Relative priority of priority 1 commands from port 0.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR45_P0PRI1   (8U)          //!< Bit position for DDR_CR45_P0PRI1.
#define BM_DDR_CR45_P0PRI1   (0x00000F00U) //!< Bit mask for DDR_CR45_P0PRI1.
#define BS_DDR_CR45_P0PRI1   (4U)          //!< Bit field size in bits for DDR_CR45_P0PRI1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR45_P0PRI1 field.
#define BR_DDR_CR45_P0PRI1   (HW_DDR_CR45.B.P0PRI1)
#endif

//! @brief Format value for bitfield DDR_CR45_P0PRI1.
#define BF_DDR_CR45_P0PRI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR45_P0PRI1), uint32_t) & BM_DDR_CR45_P0PRI1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0PRI1 field to a new value.
#define BW_DDR_CR45_P0PRI1(v) (HW_DDR_CR45_WR((HW_DDR_CR45_RD() & ~BM_DDR_CR45_P0PRI1) | BF_DDR_CR45_P0PRI1(v)))
#endif
//@}

/*!
 * @name Register DDR_CR45, field P0PRI2[19:16] (RW)
 *
 * Relative priority of priority 2 commands from port 0.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR45_P0PRI2   (16U)         //!< Bit position for DDR_CR45_P0PRI2.
#define BM_DDR_CR45_P0PRI2   (0x000F0000U) //!< Bit mask for DDR_CR45_P0PRI2.
#define BS_DDR_CR45_P0PRI2   (4U)          //!< Bit field size in bits for DDR_CR45_P0PRI2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR45_P0PRI2 field.
#define BR_DDR_CR45_P0PRI2   (HW_DDR_CR45.B.P0PRI2)
#endif

//! @brief Format value for bitfield DDR_CR45_P0PRI2.
#define BF_DDR_CR45_P0PRI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR45_P0PRI2), uint32_t) & BM_DDR_CR45_P0PRI2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0PRI2 field to a new value.
#define BW_DDR_CR45_P0PRI2(v) (HW_DDR_CR45_WR((HW_DDR_CR45_RD() & ~BM_DDR_CR45_P0PRI2) | BF_DDR_CR45_P0PRI2(v)))
#endif
//@}

/*!
 * @name Register DDR_CR45, field P0PRI3[27:24] (RW)
 *
 * Relative priority of priority 3 commands from port 0.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR45_P0PRI3   (24U)         //!< Bit position for DDR_CR45_P0PRI3.
#define BM_DDR_CR45_P0PRI3   (0x0F000000U) //!< Bit mask for DDR_CR45_P0PRI3.
#define BS_DDR_CR45_P0PRI3   (4U)          //!< Bit field size in bits for DDR_CR45_P0PRI3.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR45_P0PRI3 field.
#define BR_DDR_CR45_P0PRI3   (HW_DDR_CR45.B.P0PRI3)
#endif

//! @brief Format value for bitfield DDR_CR45_P0PRI3.
#define BF_DDR_CR45_P0PRI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR45_P0PRI3), uint32_t) & BM_DDR_CR45_P0PRI3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0PRI3 field to a new value.
#define BW_DDR_CR45_P0PRI3(v) (HW_DDR_CR45_WR((HW_DDR_CR45_RD() & ~BM_DDR_CR45_P0PRI3) | BF_DDR_CR45_P0PRI3(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR46 - DDR Control Register 46
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR46 - DDR Control Register 46 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr46
{
    uint32_t U;
    struct _hw_ddr_cr46_bitfields
    {
        uint32_t P0ORD : 2;            //!< [1:0] Port 0 Order
        uint32_t RESERVED0 : 6;        //!< [7:2] Reserved
        uint32_t P0PRIRLX : 10;        //!< [17:8] Port 0 Priority Relax
        uint32_t RESERVED1 : 6;        //!< [23:18] Reserved
        uint32_t P1PRI0 : 4;           //!< [27:24] Port 1 Priority 0 commands
        uint32_t RESERVED2 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr46_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR46 register
 */
//@{
#define HW_DDR_CR46_ADDR         (REGS_DDR_BASE + 0xB8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR46              (*(__IO hw_ddr_cr46_t *) HW_DDR_CR46_ADDR)
#define HW_DDR_CR46_RD()         (HW_DDR_CR46.U)
#define HW_DDR_CR46_WR(v)        (HW_DDR_CR46.U = (v))
#define HW_DDR_CR46_SET(v)       (HW_DDR_CR46_WR(HW_DDR_CR46_RD() |  (v)))
#define HW_DDR_CR46_CLR(v)       (HW_DDR_CR46_WR(HW_DDR_CR46_RD() & ~(v)))
#define HW_DDR_CR46_TOG(v)       (HW_DDR_CR46_WR(HW_DDR_CR46_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR46 bitfields
 */

/*!
 * @name Register DDR_CR46, field P0ORD[1:0] (RW)
 *
 * Reassigned port order for port 0. ahbY_port_ordering parameters are used to
 * set this new scan order. If the three ahbY_port_ordering parameters are
 * programmed with unique values, then the scan order will be modified to proceed
 * sequentially in this new order. If any of the port ordering parameters have the same
 * value, then those ports will still be equal in the arbitration test. In this
 * case, the port number will select between these ports, with the lower-numbered
 * port automatically being selected first.
 *
 * Values:
 * - 00 - Highest listing in the scan order
 * - 01 - ------
 * - 10 - ------
 * - 11 - Lowest listing in the scan order
 */
//@{
#define BP_DDR_CR46_P0ORD    (0U)          //!< Bit position for DDR_CR46_P0ORD.
#define BM_DDR_CR46_P0ORD    (0x00000003U) //!< Bit mask for DDR_CR46_P0ORD.
#define BS_DDR_CR46_P0ORD    (2U)          //!< Bit field size in bits for DDR_CR46_P0ORD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR46_P0ORD field.
#define BR_DDR_CR46_P0ORD    (HW_DDR_CR46.B.P0ORD)
#endif

//! @brief Format value for bitfield DDR_CR46_P0ORD.
#define BF_DDR_CR46_P0ORD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR46_P0ORD), uint32_t) & BM_DDR_CR46_P0ORD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0ORD field to a new value.
#define BW_DDR_CR46_P0ORD(v) (HW_DDR_CR46_WR((HW_DDR_CR46_RD() & ~BM_DDR_CR46_P0ORD) | BF_DDR_CR46_P0ORD(v)))
#endif
//@}

/*!
 * @name Register DDR_CR46, field P0PRIRLX[17:8] (RW)
 *
 * Counter value to trigger prioity relax on port 0.
 */
//@{
#define BP_DDR_CR46_P0PRIRLX (8U)          //!< Bit position for DDR_CR46_P0PRIRLX.
#define BM_DDR_CR46_P0PRIRLX (0x0003FF00U) //!< Bit mask for DDR_CR46_P0PRIRLX.
#define BS_DDR_CR46_P0PRIRLX (10U)         //!< Bit field size in bits for DDR_CR46_P0PRIRLX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR46_P0PRIRLX field.
#define BR_DDR_CR46_P0PRIRLX (HW_DDR_CR46.B.P0PRIRLX)
#endif

//! @brief Format value for bitfield DDR_CR46_P0PRIRLX.
#define BF_DDR_CR46_P0PRIRLX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR46_P0PRIRLX), uint32_t) & BM_DDR_CR46_P0PRIRLX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P0PRIRLX field to a new value.
#define BW_DDR_CR46_P0PRIRLX(v) (HW_DDR_CR46_WR((HW_DDR_CR46_RD() & ~BM_DDR_CR46_P0PRIRLX) | BF_DDR_CR46_P0PRIRLX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR46, field P1PRI0[27:24] (RW)
 *
 * Relative priority of priority 0 commands from port 1.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR46_P1PRI0   (24U)         //!< Bit position for DDR_CR46_P1PRI0.
#define BM_DDR_CR46_P1PRI0   (0x0F000000U) //!< Bit mask for DDR_CR46_P1PRI0.
#define BS_DDR_CR46_P1PRI0   (4U)          //!< Bit field size in bits for DDR_CR46_P1PRI0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR46_P1PRI0 field.
#define BR_DDR_CR46_P1PRI0   (HW_DDR_CR46.B.P1PRI0)
#endif

//! @brief Format value for bitfield DDR_CR46_P1PRI0.
#define BF_DDR_CR46_P1PRI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR46_P1PRI0), uint32_t) & BM_DDR_CR46_P1PRI0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1PRI0 field to a new value.
#define BW_DDR_CR46_P1PRI0(v) (HW_DDR_CR46_WR((HW_DDR_CR46_RD() & ~BM_DDR_CR46_P1PRI0) | BF_DDR_CR46_P1PRI0(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR47 - DDR Control Register 47
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR47 - DDR Control Register 47 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr47
{
    uint32_t U;
    struct _hw_ddr_cr47_bitfields
    {
        uint32_t P1PRI1 : 4;           //!< [3:0] Port 1 Priority 1 commands
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t P1PRI2 : 4;           //!< [11:8] Port 1 Priority 2 commands
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t P1PRI3 : 4;           //!< [19:16] Port 1 Priority 3 commands
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t P1ORD : 2;            //!< [25:24] Port 1 Order
        uint32_t RESERVED3 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_cr47_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR47 register
 */
//@{
#define HW_DDR_CR47_ADDR         (REGS_DDR_BASE + 0xBCU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR47              (*(__IO hw_ddr_cr47_t *) HW_DDR_CR47_ADDR)
#define HW_DDR_CR47_RD()         (HW_DDR_CR47.U)
#define HW_DDR_CR47_WR(v)        (HW_DDR_CR47.U = (v))
#define HW_DDR_CR47_SET(v)       (HW_DDR_CR47_WR(HW_DDR_CR47_RD() |  (v)))
#define HW_DDR_CR47_CLR(v)       (HW_DDR_CR47_WR(HW_DDR_CR47_RD() & ~(v)))
#define HW_DDR_CR47_TOG(v)       (HW_DDR_CR47_WR(HW_DDR_CR47_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR47 bitfields
 */

/*!
 * @name Register DDR_CR47, field P1PRI1[3:0] (RW)
 *
 * Relative priority of priority 1 commands from port 1.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR47_P1PRI1   (0U)          //!< Bit position for DDR_CR47_P1PRI1.
#define BM_DDR_CR47_P1PRI1   (0x0000000FU) //!< Bit mask for DDR_CR47_P1PRI1.
#define BS_DDR_CR47_P1PRI1   (4U)          //!< Bit field size in bits for DDR_CR47_P1PRI1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR47_P1PRI1 field.
#define BR_DDR_CR47_P1PRI1   (HW_DDR_CR47.B.P1PRI1)
#endif

//! @brief Format value for bitfield DDR_CR47_P1PRI1.
#define BF_DDR_CR47_P1PRI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR47_P1PRI1), uint32_t) & BM_DDR_CR47_P1PRI1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1PRI1 field to a new value.
#define BW_DDR_CR47_P1PRI1(v) (HW_DDR_CR47_WR((HW_DDR_CR47_RD() & ~BM_DDR_CR47_P1PRI1) | BF_DDR_CR47_P1PRI1(v)))
#endif
//@}

/*!
 * @name Register DDR_CR47, field P1PRI2[11:8] (RW)
 *
 * Relative priority of priority 2 commands from port 1.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR47_P1PRI2   (8U)          //!< Bit position for DDR_CR47_P1PRI2.
#define BM_DDR_CR47_P1PRI2   (0x00000F00U) //!< Bit mask for DDR_CR47_P1PRI2.
#define BS_DDR_CR47_P1PRI2   (4U)          //!< Bit field size in bits for DDR_CR47_P1PRI2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR47_P1PRI2 field.
#define BR_DDR_CR47_P1PRI2   (HW_DDR_CR47.B.P1PRI2)
#endif

//! @brief Format value for bitfield DDR_CR47_P1PRI2.
#define BF_DDR_CR47_P1PRI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR47_P1PRI2), uint32_t) & BM_DDR_CR47_P1PRI2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1PRI2 field to a new value.
#define BW_DDR_CR47_P1PRI2(v) (HW_DDR_CR47_WR((HW_DDR_CR47_RD() & ~BM_DDR_CR47_P1PRI2) | BF_DDR_CR47_P1PRI2(v)))
#endif
//@}

/*!
 * @name Register DDR_CR47, field P1PRI3[19:16] (RW)
 *
 * Relative priority of priority 3 commands from port 1.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR47_P1PRI3   (16U)         //!< Bit position for DDR_CR47_P1PRI3.
#define BM_DDR_CR47_P1PRI3   (0x000F0000U) //!< Bit mask for DDR_CR47_P1PRI3.
#define BS_DDR_CR47_P1PRI3   (4U)          //!< Bit field size in bits for DDR_CR47_P1PRI3.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR47_P1PRI3 field.
#define BR_DDR_CR47_P1PRI3   (HW_DDR_CR47.B.P1PRI3)
#endif

//! @brief Format value for bitfield DDR_CR47_P1PRI3.
#define BF_DDR_CR47_P1PRI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR47_P1PRI3), uint32_t) & BM_DDR_CR47_P1PRI3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1PRI3 field to a new value.
#define BW_DDR_CR47_P1PRI3(v) (HW_DDR_CR47_WR((HW_DDR_CR47_RD() & ~BM_DDR_CR47_P1PRI3) | BF_DDR_CR47_P1PRI3(v)))
#endif
//@}

/*!
 * @name Register DDR_CR47, field P1ORD[25:24] (RW)
 *
 * Reassigned port order for port 1. ahbY_port_ordering parameters are used to
 * set this new scan order. If the three ahbY_port_ordering parameters are
 * programmed with unique values, then the scan order will be modified to proceed
 * sequentially in this new order. If any of the port ordering parameters have the same
 * value, then those ports will still be equal in the arbitration test. In this
 * case, the port number will select between these ports, with the lower-numbered
 * port automatically being selected first.
 *
 * Values:
 * - 00 - Highest listing in the scan order
 * - 01 -
 * - 10 -
 * - 11 - Lowest listing in the scan order
 */
//@{
#define BP_DDR_CR47_P1ORD    (24U)         //!< Bit position for DDR_CR47_P1ORD.
#define BM_DDR_CR47_P1ORD    (0x03000000U) //!< Bit mask for DDR_CR47_P1ORD.
#define BS_DDR_CR47_P1ORD    (2U)          //!< Bit field size in bits for DDR_CR47_P1ORD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR47_P1ORD field.
#define BR_DDR_CR47_P1ORD    (HW_DDR_CR47.B.P1ORD)
#endif

//! @brief Format value for bitfield DDR_CR47_P1ORD.
#define BF_DDR_CR47_P1ORD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR47_P1ORD), uint32_t) & BM_DDR_CR47_P1ORD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1ORD field to a new value.
#define BW_DDR_CR47_P1ORD(v) (HW_DDR_CR47_WR((HW_DDR_CR47_RD() & ~BM_DDR_CR47_P1ORD) | BF_DDR_CR47_P1ORD(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR48 - DDR Control Register 48
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR48 - DDR Control Register 48 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr48
{
    uint32_t U;
    struct _hw_ddr_cr48_bitfields
    {
        uint32_t P1PRIRLX : 10;        //!< [9:0] Port 1 Priority Relax
        uint32_t RESERVED0 : 6;        //!< [15:10] Reserved
        uint32_t P2PRI0 : 4;           //!< [19:16] Port 2 Priority 0 commands
        uint32_t RESERVED1 : 4;        //!< [23:20] Reserved
        uint32_t P2PRI1 : 4;           //!< [27:24] Port 2 Priority 1 commands
        uint32_t RESERVED2 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr48_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR48 register
 */
//@{
#define HW_DDR_CR48_ADDR         (REGS_DDR_BASE + 0xC0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR48              (*(__IO hw_ddr_cr48_t *) HW_DDR_CR48_ADDR)
#define HW_DDR_CR48_RD()         (HW_DDR_CR48.U)
#define HW_DDR_CR48_WR(v)        (HW_DDR_CR48.U = (v))
#define HW_DDR_CR48_SET(v)       (HW_DDR_CR48_WR(HW_DDR_CR48_RD() |  (v)))
#define HW_DDR_CR48_CLR(v)       (HW_DDR_CR48_WR(HW_DDR_CR48_RD() & ~(v)))
#define HW_DDR_CR48_TOG(v)       (HW_DDR_CR48_WR(HW_DDR_CR48_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR48 bitfields
 */

/*!
 * @name Register DDR_CR48, field P1PRIRLX[9:0] (RW)
 *
 * Counter value to trigger priority relax on port 1.
 */
//@{
#define BP_DDR_CR48_P1PRIRLX (0U)          //!< Bit position for DDR_CR48_P1PRIRLX.
#define BM_DDR_CR48_P1PRIRLX (0x000003FFU) //!< Bit mask for DDR_CR48_P1PRIRLX.
#define BS_DDR_CR48_P1PRIRLX (10U)         //!< Bit field size in bits for DDR_CR48_P1PRIRLX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR48_P1PRIRLX field.
#define BR_DDR_CR48_P1PRIRLX (HW_DDR_CR48.B.P1PRIRLX)
#endif

//! @brief Format value for bitfield DDR_CR48_P1PRIRLX.
#define BF_DDR_CR48_P1PRIRLX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR48_P1PRIRLX), uint32_t) & BM_DDR_CR48_P1PRIRLX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P1PRIRLX field to a new value.
#define BW_DDR_CR48_P1PRIRLX(v) (HW_DDR_CR48_WR((HW_DDR_CR48_RD() & ~BM_DDR_CR48_P1PRIRLX) | BF_DDR_CR48_P1PRIRLX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR48, field P2PRI0[19:16] (RW)
 *
 * Relative priority of priority 0 commands from port 2.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR48_P2PRI0   (16U)         //!< Bit position for DDR_CR48_P2PRI0.
#define BM_DDR_CR48_P2PRI0   (0x000F0000U) //!< Bit mask for DDR_CR48_P2PRI0.
#define BS_DDR_CR48_P2PRI0   (4U)          //!< Bit field size in bits for DDR_CR48_P2PRI0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR48_P2PRI0 field.
#define BR_DDR_CR48_P2PRI0   (HW_DDR_CR48.B.P2PRI0)
#endif

//! @brief Format value for bitfield DDR_CR48_P2PRI0.
#define BF_DDR_CR48_P2PRI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR48_P2PRI0), uint32_t) & BM_DDR_CR48_P2PRI0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2PRI0 field to a new value.
#define BW_DDR_CR48_P2PRI0(v) (HW_DDR_CR48_WR((HW_DDR_CR48_RD() & ~BM_DDR_CR48_P2PRI0) | BF_DDR_CR48_P2PRI0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR48, field P2PRI1[27:24] (RW)
 *
 * Relative priority of priority 1 commands from port 2.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR48_P2PRI1   (24U)         //!< Bit position for DDR_CR48_P2PRI1.
#define BM_DDR_CR48_P2PRI1   (0x0F000000U) //!< Bit mask for DDR_CR48_P2PRI1.
#define BS_DDR_CR48_P2PRI1   (4U)          //!< Bit field size in bits for DDR_CR48_P2PRI1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR48_P2PRI1 field.
#define BR_DDR_CR48_P2PRI1   (HW_DDR_CR48.B.P2PRI1)
#endif

//! @brief Format value for bitfield DDR_CR48_P2PRI1.
#define BF_DDR_CR48_P2PRI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR48_P2PRI1), uint32_t) & BM_DDR_CR48_P2PRI1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2PRI1 field to a new value.
#define BW_DDR_CR48_P2PRI1(v) (HW_DDR_CR48_WR((HW_DDR_CR48_RD() & ~BM_DDR_CR48_P2PRI1) | BF_DDR_CR48_P2PRI1(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR49 - DDR Control Register 49
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR49 - DDR Control Register 49 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr49
{
    uint32_t U;
    struct _hw_ddr_cr49_bitfields
    {
        uint32_t P2PRI2 : 4;           //!< [3:0] Port 2 Priority 2 commands
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t P2PRI3 : 4;           //!< [11:8] Port 2 Priority 3 commands
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t P2ORD : 2;            //!< [17:16] Port 2 Order
        uint32_t RESERVED2 : 14;       //!< [31:18] Reserved
    } B;
} hw_ddr_cr49_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR49 register
 */
//@{
#define HW_DDR_CR49_ADDR         (REGS_DDR_BASE + 0xC4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR49              (*(__IO hw_ddr_cr49_t *) HW_DDR_CR49_ADDR)
#define HW_DDR_CR49_RD()         (HW_DDR_CR49.U)
#define HW_DDR_CR49_WR(v)        (HW_DDR_CR49.U = (v))
#define HW_DDR_CR49_SET(v)       (HW_DDR_CR49_WR(HW_DDR_CR49_RD() |  (v)))
#define HW_DDR_CR49_CLR(v)       (HW_DDR_CR49_WR(HW_DDR_CR49_RD() & ~(v)))
#define HW_DDR_CR49_TOG(v)       (HW_DDR_CR49_WR(HW_DDR_CR49_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR49 bitfields
 */

/*!
 * @name Register DDR_CR49, field P2PRI2[3:0] (RW)
 *
 * Relative priority of priority 2 commands from port 2.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR49_P2PRI2   (0U)          //!< Bit position for DDR_CR49_P2PRI2.
#define BM_DDR_CR49_P2PRI2   (0x0000000FU) //!< Bit mask for DDR_CR49_P2PRI2.
#define BS_DDR_CR49_P2PRI2   (4U)          //!< Bit field size in bits for DDR_CR49_P2PRI2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR49_P2PRI2 field.
#define BR_DDR_CR49_P2PRI2   (HW_DDR_CR49.B.P2PRI2)
#endif

//! @brief Format value for bitfield DDR_CR49_P2PRI2.
#define BF_DDR_CR49_P2PRI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR49_P2PRI2), uint32_t) & BM_DDR_CR49_P2PRI2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2PRI2 field to a new value.
#define BW_DDR_CR49_P2PRI2(v) (HW_DDR_CR49_WR((HW_DDR_CR49_RD() & ~BM_DDR_CR49_P2PRI2) | BF_DDR_CR49_P2PRI2(v)))
#endif
//@}

/*!
 * @name Register DDR_CR49, field P2PRI3[11:8] (RW)
 *
 * Relative priority of priority 3 commands from port 2.
 *
 * Values:
 * - 0000 - Lowest
 * - 0001 - -----
 * - 1110 - -----
 * - 1111 - Highest
 */
//@{
#define BP_DDR_CR49_P2PRI3   (8U)          //!< Bit position for DDR_CR49_P2PRI3.
#define BM_DDR_CR49_P2PRI3   (0x00000F00U) //!< Bit mask for DDR_CR49_P2PRI3.
#define BS_DDR_CR49_P2PRI3   (4U)          //!< Bit field size in bits for DDR_CR49_P2PRI3.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR49_P2PRI3 field.
#define BR_DDR_CR49_P2PRI3   (HW_DDR_CR49.B.P2PRI3)
#endif

//! @brief Format value for bitfield DDR_CR49_P2PRI3.
#define BF_DDR_CR49_P2PRI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR49_P2PRI3), uint32_t) & BM_DDR_CR49_P2PRI3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2PRI3 field to a new value.
#define BW_DDR_CR49_P2PRI3(v) (HW_DDR_CR49_WR((HW_DDR_CR49_RD() & ~BM_DDR_CR49_P2PRI3) | BF_DDR_CR49_P2PRI3(v)))
#endif
//@}

/*!
 * @name Register DDR_CR49, field P2ORD[17:16] (RW)
 *
 * Reassigned port order for port 2. ahbY_port_ordering parameters are used to
 * set this new scan order. If the three ahbY_port_ordering parameters are
 * programmed with unique values, then the scan order will be modified to proceed
 * sequentially in this new order. If any of the port ordering parameters have the same
 * value, then those ports will still be equal in the arbitration test. In this
 * case, the port number will select between these ports, with the lower-numbered
 * port automatically being selected first.
 *
 * Values:
 * - 00 - Highest listing in the scan order
 * - 01 - -----
 * - 10 - -----
 * - 11 - Lowest listing in the scan order
 */
//@{
#define BP_DDR_CR49_P2ORD    (16U)         //!< Bit position for DDR_CR49_P2ORD.
#define BM_DDR_CR49_P2ORD    (0x00030000U) //!< Bit mask for DDR_CR49_P2ORD.
#define BS_DDR_CR49_P2ORD    (2U)          //!< Bit field size in bits for DDR_CR49_P2ORD.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR49_P2ORD field.
#define BR_DDR_CR49_P2ORD    (HW_DDR_CR49.B.P2ORD)
#endif

//! @brief Format value for bitfield DDR_CR49_P2ORD.
#define BF_DDR_CR49_P2ORD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR49_P2ORD), uint32_t) & BM_DDR_CR49_P2ORD)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2ORD field to a new value.
#define BW_DDR_CR49_P2ORD(v) (HW_DDR_CR49_WR((HW_DDR_CR49_RD() & ~BM_DDR_CR49_P2ORD) | BF_DDR_CR49_P2ORD(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR50 - DDR Control Register 50
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR50 - DDR Control Register 50 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr50
{
    uint32_t U;
    struct _hw_ddr_cr50_bitfields
    {
        uint32_t P2PRIRLX : 10;        //!< [9:0] Port 2 Priority Relax
        uint32_t RESERVED0 : 6;        //!< [15:10] Reserved
        uint32_t CLKSTATUS : 1;        //!< [16] Clock Status
        uint32_t RESERVED1 : 15;       //!< [31:17] Reserved
    } B;
} hw_ddr_cr50_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR50 register
 */
//@{
#define HW_DDR_CR50_ADDR         (REGS_DDR_BASE + 0xC8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR50              (*(__IO hw_ddr_cr50_t *) HW_DDR_CR50_ADDR)
#define HW_DDR_CR50_RD()         (HW_DDR_CR50.U)
#define HW_DDR_CR50_WR(v)        (HW_DDR_CR50.U = (v))
#define HW_DDR_CR50_SET(v)       (HW_DDR_CR50_WR(HW_DDR_CR50_RD() |  (v)))
#define HW_DDR_CR50_CLR(v)       (HW_DDR_CR50_WR(HW_DDR_CR50_RD() & ~(v)))
#define HW_DDR_CR50_TOG(v)       (HW_DDR_CR50_WR(HW_DDR_CR50_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR50 bitfields
 */

/*!
 * @name Register DDR_CR50, field P2PRIRLX[9:0] (RW)
 *
 * Counter value to trigger priority relax on port 2.
 */
//@{
#define BP_DDR_CR50_P2PRIRLX (0U)          //!< Bit position for DDR_CR50_P2PRIRLX.
#define BM_DDR_CR50_P2PRIRLX (0x000003FFU) //!< Bit mask for DDR_CR50_P2PRIRLX.
#define BS_DDR_CR50_P2PRIRLX (10U)         //!< Bit field size in bits for DDR_CR50_P2PRIRLX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR50_P2PRIRLX field.
#define BR_DDR_CR50_P2PRIRLX (HW_DDR_CR50.B.P2PRIRLX)
#endif

//! @brief Format value for bitfield DDR_CR50_P2PRIRLX.
#define BF_DDR_CR50_P2PRIRLX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR50_P2PRIRLX), uint32_t) & BM_DDR_CR50_P2PRIRLX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the P2PRIRLX field to a new value.
#define BW_DDR_CR50_P2PRIRLX(v) (HW_DDR_CR50_WR((HW_DDR_CR50_RD() & ~BM_DDR_CR50_P2PRIRLX) | BF_DDR_CR50_P2PRIRLX(v)))
#endif
//@}

/*!
 * @name Register DDR_CR50, field CLKSTATUS[16] (RO)
 *
 * Register access to clkstatus signal.
 *
 * Values:
 * - 0 - Disabled
 * - 1 - Enabled
 */
//@{
#define BP_DDR_CR50_CLKSTATUS (16U)        //!< Bit position for DDR_CR50_CLKSTATUS.
#define BM_DDR_CR50_CLKSTATUS (0x00010000U) //!< Bit mask for DDR_CR50_CLKSTATUS.
#define BS_DDR_CR50_CLKSTATUS (1U)         //!< Bit field size in bits for DDR_CR50_CLKSTATUS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR50_CLKSTATUS field.
#define BR_DDR_CR50_CLKSTATUS (BITBAND_ACCESS32(HW_DDR_CR50_ADDR, BP_DDR_CR50_CLKSTATUS))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR51 - DDR Control Register 51
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR51 - DDR Control Register 51 (RW)
 *
 * Reset value: 0x00000400U
 */
typedef union _hw_ddr_cr51
{
    uint32_t U;
    struct _hw_ddr_cr51_bitfields
    {
        uint32_t DLLRSTDLY : 16;       //!< [15:0] DLL Reset Delay
        uint32_t DLLRADLY : 8;         //!< [23:16] DLL Reset Adjust Delay
        uint32_t PHYWRLAT : 4;         //!< [27:24] PHY Write Latency
        uint32_t RESERVED0 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr51_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR51 register
 */
//@{
#define HW_DDR_CR51_ADDR         (REGS_DDR_BASE + 0xCCU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR51              (*(__IO hw_ddr_cr51_t *) HW_DDR_CR51_ADDR)
#define HW_DDR_CR51_RD()         (HW_DDR_CR51.U)
#define HW_DDR_CR51_WR(v)        (HW_DDR_CR51.U = (v))
#define HW_DDR_CR51_SET(v)       (HW_DDR_CR51_WR(HW_DDR_CR51_RD() |  (v)))
#define HW_DDR_CR51_CLR(v)       (HW_DDR_CR51_WR(HW_DDR_CR51_RD() & ~(v)))
#define HW_DDR_CR51_TOG(v)       (HW_DDR_CR51_WR(HW_DDR_CR51_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR51 bitfields
 */

/*!
 * @name Register DDR_CR51, field DLLRSTDLY[15:0] (RW)
 *
 * Minimum number of cycles required for DLL reset.
 */
//@{
#define BP_DDR_CR51_DLLRSTDLY (0U)         //!< Bit position for DDR_CR51_DLLRSTDLY.
#define BM_DDR_CR51_DLLRSTDLY (0x0000FFFFU) //!< Bit mask for DDR_CR51_DLLRSTDLY.
#define BS_DDR_CR51_DLLRSTDLY (16U)        //!< Bit field size in bits for DDR_CR51_DLLRSTDLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR51_DLLRSTDLY field.
#define BR_DDR_CR51_DLLRSTDLY (HW_DDR_CR51.B.DLLRSTDLY)
#endif

//! @brief Format value for bitfield DDR_CR51_DLLRSTDLY.
#define BF_DDR_CR51_DLLRSTDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR51_DLLRSTDLY), uint32_t) & BM_DDR_CR51_DLLRSTDLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DLLRSTDLY field to a new value.
#define BW_DDR_CR51_DLLRSTDLY(v) (HW_DDR_CR51_WR((HW_DDR_CR51_RD() & ~BM_DDR_CR51_DLLRSTDLY) | BF_DDR_CR51_DLLRSTDLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR51, field DLLRADLY[23:16] (RW)
 *
 * Minimum number of cycles after setting master delay in DLL until reset is
 * released.
 */
//@{
#define BP_DDR_CR51_DLLRADLY (16U)         //!< Bit position for DDR_CR51_DLLRADLY.
#define BM_DDR_CR51_DLLRADLY (0x00FF0000U) //!< Bit mask for DDR_CR51_DLLRADLY.
#define BS_DDR_CR51_DLLRADLY (8U)          //!< Bit field size in bits for DDR_CR51_DLLRADLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR51_DLLRADLY field.
#define BR_DDR_CR51_DLLRADLY (HW_DDR_CR51.B.DLLRADLY)
#endif

//! @brief Format value for bitfield DDR_CR51_DLLRADLY.
#define BF_DDR_CR51_DLLRADLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR51_DLLRADLY), uint32_t) & BM_DDR_CR51_DLLRADLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the DLLRADLY field to a new value.
#define BW_DDR_CR51_DLLRADLY(v) (HW_DDR_CR51_WR((HW_DDR_CR51_RD() & ~BM_DDR_CR51_DLLRADLY) | BF_DDR_CR51_DLLRADLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR51, field PHYWRLAT[27:24] (RO)
 *
 * Holds the calculated value of the t phy_wrlat timing parameter, the number of
 * DFI PHY clock cycles between when a write command is sent on the DFI control
 * interface and when the dfi_wrdata_en signal is asserted. This parameter is
 * used to adjust the dfi_wrdata_en signal timing. t dfi_phy_wrlat = t
 * dfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable minus WRLAT_WIDTH'h3 Values of t
 * dfi_phy_wrlat_base + wrlat_adj that are less than 3 are not supported. All DFI timing
 * parameters must be programmed relative to the DFI clock.
 */
//@{
#define BP_DDR_CR51_PHYWRLAT (24U)         //!< Bit position for DDR_CR51_PHYWRLAT.
#define BM_DDR_CR51_PHYWRLAT (0x0F000000U) //!< Bit mask for DDR_CR51_PHYWRLAT.
#define BS_DDR_CR51_PHYWRLAT (4U)          //!< Bit field size in bits for DDR_CR51_PHYWRLAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR51_PHYWRLAT field.
#define BR_DDR_CR51_PHYWRLAT (HW_DDR_CR51.B.PHYWRLAT)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR52 - DDR Control Register 52
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR52 - DDR Control Register 52 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr52
{
    uint32_t U;
    struct _hw_ddr_cr52_bitfields
    {
        uint32_t PYWRLTBS : 4;         //!< [3:0] PHY Write Latency Base
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t PHYRDLAT : 4;         //!< [11:8] PHY Read Latency
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t RDDATAEN : 4;         //!< [19:16] Read Data Enable
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t RDDTENBAS : 4;        //!< [27:24] Read Data Enable Base
        uint32_t RESERVED3 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr52_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR52 register
 */
//@{
#define HW_DDR_CR52_ADDR         (REGS_DDR_BASE + 0xD0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR52              (*(__IO hw_ddr_cr52_t *) HW_DDR_CR52_ADDR)
#define HW_DDR_CR52_RD()         (HW_DDR_CR52.U)
#define HW_DDR_CR52_WR(v)        (HW_DDR_CR52.U = (v))
#define HW_DDR_CR52_SET(v)       (HW_DDR_CR52_WR(HW_DDR_CR52_RD() |  (v)))
#define HW_DDR_CR52_CLR(v)       (HW_DDR_CR52_WR(HW_DDR_CR52_RD() & ~(v)))
#define HW_DDR_CR52_TOG(v)       (HW_DDR_CR52_WR(HW_DDR_CR52_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR52 bitfields
 */

/*!
 * @name Register DDR_CR52, field PYWRLTBS[3:0] (RW)
 *
 * Sets DFI base value for the t PHY_RWLAT timing parameter.
 */
//@{
#define BP_DDR_CR52_PYWRLTBS (0U)          //!< Bit position for DDR_CR52_PYWRLTBS.
#define BM_DDR_CR52_PYWRLTBS (0x0000000FU) //!< Bit mask for DDR_CR52_PYWRLTBS.
#define BS_DDR_CR52_PYWRLTBS (4U)          //!< Bit field size in bits for DDR_CR52_PYWRLTBS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR52_PYWRLTBS field.
#define BR_DDR_CR52_PYWRLTBS (HW_DDR_CR52.B.PYWRLTBS)
#endif

//! @brief Format value for bitfield DDR_CR52_PYWRLTBS.
#define BF_DDR_CR52_PYWRLTBS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR52_PYWRLTBS), uint32_t) & BM_DDR_CR52_PYWRLTBS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PYWRLTBS field to a new value.
#define BW_DDR_CR52_PYWRLTBS(v) (HW_DDR_CR52_WR((HW_DDR_CR52_RD() & ~BM_DDR_CR52_PYWRLTBS) | BF_DDR_CR52_PYWRLTBS(v)))
#endif
//@}

/*!
 * @name Register DDR_CR52, field PHYRDLAT[11:8] (RW)
 *
 * Holds the t PHY_RDLAT timing parameter.
 */
//@{
#define BP_DDR_CR52_PHYRDLAT (8U)          //!< Bit position for DDR_CR52_PHYRDLAT.
#define BM_DDR_CR52_PHYRDLAT (0x00000F00U) //!< Bit mask for DDR_CR52_PHYRDLAT.
#define BS_DDR_CR52_PHYRDLAT (4U)          //!< Bit field size in bits for DDR_CR52_PHYRDLAT.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR52_PHYRDLAT field.
#define BR_DDR_CR52_PHYRDLAT (HW_DDR_CR52.B.PHYRDLAT)
#endif

//! @brief Format value for bitfield DDR_CR52_PHYRDLAT.
#define BF_DDR_CR52_PHYRDLAT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR52_PHYRDLAT), uint32_t) & BM_DDR_CR52_PHYRDLAT)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYRDLAT field to a new value.
#define BW_DDR_CR52_PHYRDLAT(v) (HW_DDR_CR52_WR((HW_DDR_CR52_RD() & ~BM_DDR_CR52_PHYRDLAT) | BF_DDR_CR52_PHYRDLAT(v)))
#endif
//@}

/*!
 * @name Register DDR_CR52, field RDDATAEN[19:16] (RO)
 *
 * Holds the calculated DFI t RDDATA_EN timing parameter.
 */
//@{
#define BP_DDR_CR52_RDDATAEN (16U)         //!< Bit position for DDR_CR52_RDDATAEN.
#define BM_DDR_CR52_RDDATAEN (0x000F0000U) //!< Bit mask for DDR_CR52_RDDATAEN.
#define BS_DDR_CR52_RDDATAEN (4U)          //!< Bit field size in bits for DDR_CR52_RDDATAEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR52_RDDATAEN field.
#define BR_DDR_CR52_RDDATAEN (HW_DDR_CR52.B.RDDATAEN)
#endif
//@}

/*!
 * @name Register DDR_CR52, field RDDTENBAS[27:24] (RW)
 *
 * Sets DFI base value for the t RDDATA_EN timing parameter.
 */
//@{
#define BP_DDR_CR52_RDDTENBAS (24U)        //!< Bit position for DDR_CR52_RDDTENBAS.
#define BM_DDR_CR52_RDDTENBAS (0x0F000000U) //!< Bit mask for DDR_CR52_RDDTENBAS.
#define BS_DDR_CR52_RDDTENBAS (4U)         //!< Bit field size in bits for DDR_CR52_RDDTENBAS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR52_RDDTENBAS field.
#define BR_DDR_CR52_RDDTENBAS (HW_DDR_CR52.B.RDDTENBAS)
#endif

//! @brief Format value for bitfield DDR_CR52_RDDTENBAS.
#define BF_DDR_CR52_RDDTENBAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR52_RDDTENBAS), uint32_t) & BM_DDR_CR52_RDDTENBAS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RDDTENBAS field to a new value.
#define BW_DDR_CR52_RDDTENBAS(v) (HW_DDR_CR52_WR((HW_DDR_CR52_RD() & ~BM_DDR_CR52_RDDTENBAS) | BF_DDR_CR52_RDDTENBAS(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR53 - DDR Control Register 53
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR53 - DDR Control Register 53 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr53
{
    uint32_t U;
    struct _hw_ddr_cr53_bitfields
    {
        uint32_t CLKDISCS : 1;         //!< [0] DRAM Clock Disable for chip select
        uint32_t RESERVED0 : 7;        //!< [7:1] Reserved
        uint32_t CRTLUPDMN : 4;        //!< [11:8] DFI CRTLUPD Minimum
        uint32_t RESERVED1 : 4;        //!< [15:12] Reserved
        uint32_t CTRLUPDMX : 14;       //!< [29:16] DFI CRTLUPD Minimum
        uint32_t RESERVED2 : 2;        //!< [31:30] Reserved
    } B;
} hw_ddr_cr53_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR53 register
 */
//@{
#define HW_DDR_CR53_ADDR         (REGS_DDR_BASE + 0xD4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR53              (*(__IO hw_ddr_cr53_t *) HW_DDR_CR53_ADDR)
#define HW_DDR_CR53_RD()         (HW_DDR_CR53.U)
#define HW_DDR_CR53_WR(v)        (HW_DDR_CR53.U = (v))
#define HW_DDR_CR53_SET(v)       (HW_DDR_CR53_WR(HW_DDR_CR53_RD() |  (v)))
#define HW_DDR_CR53_CLR(v)       (HW_DDR_CR53_WR(HW_DDR_CR53_RD() & ~(v)))
#define HW_DDR_CR53_TOG(v)       (HW_DDR_CR53_WR(HW_DDR_CR53_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR53 bitfields
 */

/*!
 * @name Register DDR_CR53, field CLKDISCS[0] (RW)
 *
 * Set value for the dfi_dram_clk_disable signal.
 *
 * Values:
 * - 0 - Memory clock active
 * - 1 - Memory clock disabled
 */
//@{
#define BP_DDR_CR53_CLKDISCS (0U)          //!< Bit position for DDR_CR53_CLKDISCS.
#define BM_DDR_CR53_CLKDISCS (0x00000001U) //!< Bit mask for DDR_CR53_CLKDISCS.
#define BS_DDR_CR53_CLKDISCS (1U)          //!< Bit field size in bits for DDR_CR53_CLKDISCS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR53_CLKDISCS field.
#define BR_DDR_CR53_CLKDISCS (BITBAND_ACCESS32(HW_DDR_CR53_ADDR, BP_DDR_CR53_CLKDISCS))
#endif

//! @brief Format value for bitfield DDR_CR53_CLKDISCS.
#define BF_DDR_CR53_CLKDISCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR53_CLKDISCS), uint32_t) & BM_DDR_CR53_CLKDISCS)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKDISCS field to a new value.
#define BW_DDR_CR53_CLKDISCS(v) (BITBAND_ACCESS32(HW_DDR_CR53_ADDR, BP_DDR_CR53_CLKDISCS) = (v))
#endif
//@}

/*!
 * @name Register DDR_CR53, field CRTLUPDMN[11:8] (RO)
 *
 * Holds the DFI t CTRLUPD_MIN timing parameter.
 */
//@{
#define BP_DDR_CR53_CRTLUPDMN (8U)         //!< Bit position for DDR_CR53_CRTLUPDMN.
#define BM_DDR_CR53_CRTLUPDMN (0x00000F00U) //!< Bit mask for DDR_CR53_CRTLUPDMN.
#define BS_DDR_CR53_CRTLUPDMN (4U)         //!< Bit field size in bits for DDR_CR53_CRTLUPDMN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR53_CRTLUPDMN field.
#define BR_DDR_CR53_CRTLUPDMN (HW_DDR_CR53.B.CRTLUPDMN)
#endif
//@}

/*!
 * @name Register DDR_CR53, field CTRLUPDMX[29:16] (RW)
 *
 * Contains the DFI t TRLUPD_MAX timing parameter.
 */
//@{
#define BP_DDR_CR53_CTRLUPDMX (16U)        //!< Bit position for DDR_CR53_CTRLUPDMX.
#define BM_DDR_CR53_CTRLUPDMX (0x3FFF0000U) //!< Bit mask for DDR_CR53_CTRLUPDMX.
#define BS_DDR_CR53_CTRLUPDMX (14U)        //!< Bit field size in bits for DDR_CR53_CTRLUPDMX.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR53_CTRLUPDMX field.
#define BR_DDR_CR53_CTRLUPDMX (HW_DDR_CR53.B.CTRLUPDMX)
#endif

//! @brief Format value for bitfield DDR_CR53_CTRLUPDMX.
#define BF_DDR_CR53_CTRLUPDMX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR53_CTRLUPDMX), uint32_t) & BM_DDR_CR53_CTRLUPDMX)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CTRLUPDMX field to a new value.
#define BW_DDR_CR53_CTRLUPDMX(v) (HW_DDR_CR53_WR((HW_DDR_CR53_RD() & ~BM_DDR_CR53_CTRLUPDMX) | BF_DDR_CR53_CTRLUPDMX(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR54 - DDR Control Register 54
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR54 - DDR Control Register 54 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr54
{
    uint32_t U;
    struct _hw_ddr_cr54_bitfields
    {
        uint32_t PHYUPDTY0 : 14;       //!< [13:0] DFI PHYUPD Type 0
        uint32_t RESERVED0 : 2;        //!< [15:14] Reserved
        uint32_t PHYUPDTY1 : 14;       //!< [29:16] DFI PHYUPD Type 1
        uint32_t RESERVED1 : 2;        //!< [31:30] Reserved
    } B;
} hw_ddr_cr54_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR54 register
 */
//@{
#define HW_DDR_CR54_ADDR         (REGS_DDR_BASE + 0xD8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR54              (*(__IO hw_ddr_cr54_t *) HW_DDR_CR54_ADDR)
#define HW_DDR_CR54_RD()         (HW_DDR_CR54.U)
#define HW_DDR_CR54_WR(v)        (HW_DDR_CR54.U = (v))
#define HW_DDR_CR54_SET(v)       (HW_DDR_CR54_WR(HW_DDR_CR54_RD() |  (v)))
#define HW_DDR_CR54_CLR(v)       (HW_DDR_CR54_WR(HW_DDR_CR54_RD() & ~(v)))
#define HW_DDR_CR54_TOG(v)       (HW_DDR_CR54_WR(HW_DDR_CR54_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR54 bitfields
 */

/*!
 * @name Register DDR_CR54, field PHYUPDTY0[13:0] (RW)
 *
 * Holds the DFI t PHYUPD_TYPE0 timing parameter.
 */
//@{
#define BP_DDR_CR54_PHYUPDTY0 (0U)         //!< Bit position for DDR_CR54_PHYUPDTY0.
#define BM_DDR_CR54_PHYUPDTY0 (0x00003FFFU) //!< Bit mask for DDR_CR54_PHYUPDTY0.
#define BS_DDR_CR54_PHYUPDTY0 (14U)        //!< Bit field size in bits for DDR_CR54_PHYUPDTY0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR54_PHYUPDTY0 field.
#define BR_DDR_CR54_PHYUPDTY0 (HW_DDR_CR54.B.PHYUPDTY0)
#endif

//! @brief Format value for bitfield DDR_CR54_PHYUPDTY0.
#define BF_DDR_CR54_PHYUPDTY0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR54_PHYUPDTY0), uint32_t) & BM_DDR_CR54_PHYUPDTY0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYUPDTY0 field to a new value.
#define BW_DDR_CR54_PHYUPDTY0(v) (HW_DDR_CR54_WR((HW_DDR_CR54_RD() & ~BM_DDR_CR54_PHYUPDTY0) | BF_DDR_CR54_PHYUPDTY0(v)))
#endif
//@}

/*!
 * @name Register DDR_CR54, field PHYUPDTY1[29:16] (RW)
 *
 * Holds the DFI t PHYUPD_TYPE1 timing parameter.
 */
//@{
#define BP_DDR_CR54_PHYUPDTY1 (16U)        //!< Bit position for DDR_CR54_PHYUPDTY1.
#define BM_DDR_CR54_PHYUPDTY1 (0x3FFF0000U) //!< Bit mask for DDR_CR54_PHYUPDTY1.
#define BS_DDR_CR54_PHYUPDTY1 (14U)        //!< Bit field size in bits for DDR_CR54_PHYUPDTY1.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR54_PHYUPDTY1 field.
#define BR_DDR_CR54_PHYUPDTY1 (HW_DDR_CR54.B.PHYUPDTY1)
#endif

//! @brief Format value for bitfield DDR_CR54_PHYUPDTY1.
#define BF_DDR_CR54_PHYUPDTY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR54_PHYUPDTY1), uint32_t) & BM_DDR_CR54_PHYUPDTY1)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYUPDTY1 field to a new value.
#define BW_DDR_CR54_PHYUPDTY1(v) (HW_DDR_CR54_WR((HW_DDR_CR54_RD() & ~BM_DDR_CR54_PHYUPDTY1) | BF_DDR_CR54_PHYUPDTY1(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR55 - DDR Control Register 55
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR55 - DDR Control Register 55 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr55
{
    uint32_t U;
    struct _hw_ddr_cr55_bitfields
    {
        uint32_t PHYUPDTY2 : 14;       //!< [13:0] DFI PHYUPD TYPE2
        uint32_t RESERVED0 : 2;        //!< [15:14] Reserved
        uint32_t PHYUPDTY3 : 14;       //!< [29:16] DFI PHYUPD TYPE3
        uint32_t RESERVED1 : 2;        //!< [31:30] Reserved
    } B;
} hw_ddr_cr55_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR55 register
 */
//@{
#define HW_DDR_CR55_ADDR         (REGS_DDR_BASE + 0xDCU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR55              (*(__IO hw_ddr_cr55_t *) HW_DDR_CR55_ADDR)
#define HW_DDR_CR55_RD()         (HW_DDR_CR55.U)
#define HW_DDR_CR55_WR(v)        (HW_DDR_CR55.U = (v))
#define HW_DDR_CR55_SET(v)       (HW_DDR_CR55_WR(HW_DDR_CR55_RD() |  (v)))
#define HW_DDR_CR55_CLR(v)       (HW_DDR_CR55_WR(HW_DDR_CR55_RD() & ~(v)))
#define HW_DDR_CR55_TOG(v)       (HW_DDR_CR55_WR(HW_DDR_CR55_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR55 bitfields
 */

/*!
 * @name Register DDR_CR55, field PHYUPDTY2[13:0] (RW)
 *
 * Holds the DFI t PHYUPD_TYPE2 timing parameter.
 */
//@{
#define BP_DDR_CR55_PHYUPDTY2 (0U)         //!< Bit position for DDR_CR55_PHYUPDTY2.
#define BM_DDR_CR55_PHYUPDTY2 (0x00003FFFU) //!< Bit mask for DDR_CR55_PHYUPDTY2.
#define BS_DDR_CR55_PHYUPDTY2 (14U)        //!< Bit field size in bits for DDR_CR55_PHYUPDTY2.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR55_PHYUPDTY2 field.
#define BR_DDR_CR55_PHYUPDTY2 (HW_DDR_CR55.B.PHYUPDTY2)
#endif

//! @brief Format value for bitfield DDR_CR55_PHYUPDTY2.
#define BF_DDR_CR55_PHYUPDTY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR55_PHYUPDTY2), uint32_t) & BM_DDR_CR55_PHYUPDTY2)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYUPDTY2 field to a new value.
#define BW_DDR_CR55_PHYUPDTY2(v) (HW_DDR_CR55_WR((HW_DDR_CR55_RD() & ~BM_DDR_CR55_PHYUPDTY2) | BF_DDR_CR55_PHYUPDTY2(v)))
#endif
//@}

/*!
 * @name Register DDR_CR55, field PHYUPDTY3[29:16] (RW)
 *
 * Holds the DFI t PHYUPD_TYPE3 timing parameter.
 */
//@{
#define BP_DDR_CR55_PHYUPDTY3 (16U)        //!< Bit position for DDR_CR55_PHYUPDTY3.
#define BM_DDR_CR55_PHYUPDTY3 (0x3FFF0000U) //!< Bit mask for DDR_CR55_PHYUPDTY3.
#define BS_DDR_CR55_PHYUPDTY3 (14U)        //!< Bit field size in bits for DDR_CR55_PHYUPDTY3.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR55_PHYUPDTY3 field.
#define BR_DDR_CR55_PHYUPDTY3 (HW_DDR_CR55.B.PHYUPDTY3)
#endif

//! @brief Format value for bitfield DDR_CR55_PHYUPDTY3.
#define BF_DDR_CR55_PHYUPDTY3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR55_PHYUPDTY3), uint32_t) & BM_DDR_CR55_PHYUPDTY3)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYUPDTY3 field to a new value.
#define BW_DDR_CR55_PHYUPDTY3(v) (HW_DDR_CR55_WR((HW_DDR_CR55_RD() & ~BM_DDR_CR55_PHYUPDTY3) | BF_DDR_CR55_PHYUPDTY3(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR56 - DDR Control Register 56
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR56 - DDR Control Register 56 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr56
{
    uint32_t U;
    struct _hw_ddr_cr56_bitfields
    {
        uint32_t PHYUPDRESP : 14;      //!< [13:0] TDFI PHYUPDRESP parameter
        uint32_t RESERVED0 : 2;        //!< [15:14] Reserved
        uint32_t RDLATADJ : 4;         //!< [19:16] Read Latency Adjust
        uint32_t RESERVED1 : 4;        //!< [23:20] Reserved
        uint32_t WRLATADJ : 4;         //!< [27:24] Write Latency Adjust
        uint32_t RESERVED2 : 4;        //!< [31:28] Reserved
    } B;
} hw_ddr_cr56_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR56 register
 */
//@{
#define HW_DDR_CR56_ADDR         (REGS_DDR_BASE + 0xE0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR56              (*(__IO hw_ddr_cr56_t *) HW_DDR_CR56_ADDR)
#define HW_DDR_CR56_RD()         (HW_DDR_CR56.U)
#define HW_DDR_CR56_WR(v)        (HW_DDR_CR56.U = (v))
#define HW_DDR_CR56_SET(v)       (HW_DDR_CR56_WR(HW_DDR_CR56_RD() |  (v)))
#define HW_DDR_CR56_CLR(v)       (HW_DDR_CR56_WR(HW_DDR_CR56_RD() & ~(v)))
#define HW_DDR_CR56_TOG(v)       (HW_DDR_CR56_WR(HW_DDR_CR56_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR56 bitfields
 */

/*!
 * @name Register DDR_CR56, field PHYUPDRESP[13:0] (RW)
 *
 * Contains the DFI t PHYUPD_RESP timing parameter.
 */
//@{
#define BP_DDR_CR56_PHYUPDRESP (0U)        //!< Bit position for DDR_CR56_PHYUPDRESP.
#define BM_DDR_CR56_PHYUPDRESP (0x00003FFFU) //!< Bit mask for DDR_CR56_PHYUPDRESP.
#define BS_DDR_CR56_PHYUPDRESP (14U)       //!< Bit field size in bits for DDR_CR56_PHYUPDRESP.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR56_PHYUPDRESP field.
#define BR_DDR_CR56_PHYUPDRESP (HW_DDR_CR56.B.PHYUPDRESP)
#endif

//! @brief Format value for bitfield DDR_CR56_PHYUPDRESP.
#define BF_DDR_CR56_PHYUPDRESP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR56_PHYUPDRESP), uint32_t) & BM_DDR_CR56_PHYUPDRESP)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PHYUPDRESP field to a new value.
#define BW_DDR_CR56_PHYUPDRESP(v) (HW_DDR_CR56_WR((HW_DDR_CR56_RD() & ~BM_DDR_CR56_PHYUPDRESP) | BF_DDR_CR56_PHYUPDRESP(v)))
#endif
//@}

/*!
 * @name Register DDR_CR56, field RDLATADJ[19:16] (RW)
 *
 * Adjustment value for PHY read timing.
 */
//@{
#define BP_DDR_CR56_RDLATADJ (16U)         //!< Bit position for DDR_CR56_RDLATADJ.
#define BM_DDR_CR56_RDLATADJ (0x000F0000U) //!< Bit mask for DDR_CR56_RDLATADJ.
#define BS_DDR_CR56_RDLATADJ (4U)          //!< Bit field size in bits for DDR_CR56_RDLATADJ.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR56_RDLATADJ field.
#define BR_DDR_CR56_RDLATADJ (HW_DDR_CR56.B.RDLATADJ)
#endif

//! @brief Format value for bitfield DDR_CR56_RDLATADJ.
#define BF_DDR_CR56_RDLATADJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR56_RDLATADJ), uint32_t) & BM_DDR_CR56_RDLATADJ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RDLATADJ field to a new value.
#define BW_DDR_CR56_RDLATADJ(v) (HW_DDR_CR56_WR((HW_DDR_CR56_RD() & ~BM_DDR_CR56_RDLATADJ) | BF_DDR_CR56_RDLATADJ(v)))
#endif
//@}

/*!
 * @name Register DDR_CR56, field WRLATADJ[27:24] (RW)
 *
 * Adjustment value for PHY write timing.
 */
//@{
#define BP_DDR_CR56_WRLATADJ (24U)         //!< Bit position for DDR_CR56_WRLATADJ.
#define BM_DDR_CR56_WRLATADJ (0x0F000000U) //!< Bit mask for DDR_CR56_WRLATADJ.
#define BS_DDR_CR56_WRLATADJ (4U)          //!< Bit field size in bits for DDR_CR56_WRLATADJ.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR56_WRLATADJ field.
#define BR_DDR_CR56_WRLATADJ (HW_DDR_CR56.B.WRLATADJ)
#endif

//! @brief Format value for bitfield DDR_CR56_WRLATADJ.
#define BF_DDR_CR56_WRLATADJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR56_WRLATADJ), uint32_t) & BM_DDR_CR56_WRLATADJ)

#ifndef __LANGUAGE_ASM__
//! @brief Set the WRLATADJ field to a new value.
#define BW_DDR_CR56_WRLATADJ(v) (HW_DDR_CR56_WR((HW_DDR_CR56_RD() & ~BM_DDR_CR56_WRLATADJ) | BF_DDR_CR56_WRLATADJ(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR57 - DDR Control Register 57
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR57 - DDR Control Register 57 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr57
{
    uint32_t U;
    struct _hw_ddr_cr57_bitfields
    {
        uint32_t CMDDLY : 4;           //!< [3:0] Command Delay
        uint32_t RESERVED0 : 4;        //!< [7:4] Reserved
        uint32_t CLKDISDLY : 3;        //!< [10:8] DFI Clock Disable Delay
        uint32_t RESERVED1 : 5;        //!< [15:11] Reserved
        uint32_t CLKENDLY : 4;         //!< [19:16] DFI Clock Enable Delay
        uint32_t RESERVED2 : 4;        //!< [23:20] Reserved
        uint32_t ODTALTEN : 1;         //!< [24] ODT Alternate Enable
        uint32_t RESERVED3 : 7;        //!< [31:25] Reserved
    } B;
} hw_ddr_cr57_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR57 register
 */
//@{
#define HW_DDR_CR57_ADDR         (REGS_DDR_BASE + 0xE4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR57              (*(__IO hw_ddr_cr57_t *) HW_DDR_CR57_ADDR)
#define HW_DDR_CR57_RD()         (HW_DDR_CR57.U)
#define HW_DDR_CR57_WR(v)        (HW_DDR_CR57.U = (v))
#define HW_DDR_CR57_SET(v)       (HW_DDR_CR57_WR(HW_DDR_CR57_RD() |  (v)))
#define HW_DDR_CR57_CLR(v)       (HW_DDR_CR57_WR(HW_DDR_CR57_RD() & ~(v)))
#define HW_DDR_CR57_TOG(v)       (HW_DDR_CR57_WR(HW_DDR_CR57_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_CR57 bitfields
 */

/*!
 * @name Register DDR_CR57, field CMDDLY[3:0] (RW)
 *
 * Delay from DFI command to memory command.
 */
//@{
#define BP_DDR_CR57_CMDDLY   (0U)          //!< Bit position for DDR_CR57_CMDDLY.
#define BM_DDR_CR57_CMDDLY   (0x0000000FU) //!< Bit mask for DDR_CR57_CMDDLY.
#define BS_DDR_CR57_CMDDLY   (4U)          //!< Bit field size in bits for DDR_CR57_CMDDLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR57_CMDDLY field.
#define BR_DDR_CR57_CMDDLY   (HW_DDR_CR57.B.CMDDLY)
#endif

//! @brief Format value for bitfield DDR_CR57_CMDDLY.
#define BF_DDR_CR57_CMDDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR57_CMDDLY), uint32_t) & BM_DDR_CR57_CMDDLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CMDDLY field to a new value.
#define BW_DDR_CR57_CMDDLY(v) (HW_DDR_CR57_WR((HW_DDR_CR57_RD() & ~BM_DDR_CR57_CMDDLY) | BF_DDR_CR57_CMDDLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR57, field CLKDISDLY[10:8] (RW)
 *
 * Delay from DFI clock disable to memory clock disenable.
 */
//@{
#define BP_DDR_CR57_CLKDISDLY (8U)         //!< Bit position for DDR_CR57_CLKDISDLY.
#define BM_DDR_CR57_CLKDISDLY (0x00000700U) //!< Bit mask for DDR_CR57_CLKDISDLY.
#define BS_DDR_CR57_CLKDISDLY (3U)         //!< Bit field size in bits for DDR_CR57_CLKDISDLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR57_CLKDISDLY field.
#define BR_DDR_CR57_CLKDISDLY (HW_DDR_CR57.B.CLKDISDLY)
#endif

//! @brief Format value for bitfield DDR_CR57_CLKDISDLY.
#define BF_DDR_CR57_CLKDISDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR57_CLKDISDLY), uint32_t) & BM_DDR_CR57_CLKDISDLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKDISDLY field to a new value.
#define BW_DDR_CR57_CLKDISDLY(v) (HW_DDR_CR57_WR((HW_DDR_CR57_RD() & ~BM_DDR_CR57_CLKDISDLY) | BF_DDR_CR57_CLKDISDLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR57, field CLKENDLY[19:16] (RW)
 *
 * Delay from DFI clock enable to memory clock enable.
 */
//@{
#define BP_DDR_CR57_CLKENDLY (16U)         //!< Bit position for DDR_CR57_CLKENDLY.
#define BM_DDR_CR57_CLKENDLY (0x000F0000U) //!< Bit mask for DDR_CR57_CLKENDLY.
#define BS_DDR_CR57_CLKENDLY (4U)          //!< Bit field size in bits for DDR_CR57_CLKENDLY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR57_CLKENDLY field.
#define BR_DDR_CR57_CLKENDLY (HW_DDR_CR57.B.CLKENDLY)
#endif

//! @brief Format value for bitfield DDR_CR57_CLKENDLY.
#define BF_DDR_CR57_CLKENDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR57_CLKENDLY), uint32_t) & BM_DDR_CR57_CLKENDLY)

#ifndef __LANGUAGE_ASM__
//! @brief Set the CLKENDLY field to a new value.
#define BW_DDR_CR57_CLKENDLY(v) (HW_DDR_CR57_WR((HW_DDR_CR57_RD() & ~BM_DDR_CR57_CLKENDLY) | BF_DDR_CR57_CLKENDLY(v)))
#endif
//@}

/*!
 * @name Register DDR_CR57, field ODTALTEN[24] (RW)
 *
 * Enable use of non-DFI odt_alt signal .
 *
 * Values:
 * - 0 - Disable
 * - 1 - Enable
 */
//@{
#define BP_DDR_CR57_ODTALTEN (24U)         //!< Bit position for DDR_CR57_ODTALTEN.
#define BM_DDR_CR57_ODTALTEN (0x01000000U) //!< Bit mask for DDR_CR57_ODTALTEN.
#define BS_DDR_CR57_ODTALTEN (1U)          //!< Bit field size in bits for DDR_CR57_ODTALTEN.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR57_ODTALTEN field.
#define BR_DDR_CR57_ODTALTEN (BITBAND_ACCESS32(HW_DDR_CR57_ADDR, BP_DDR_CR57_ODTALTEN))
#endif

//! @brief Format value for bitfield DDR_CR57_ODTALTEN.
#define BF_DDR_CR57_ODTALTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_CR57_ODTALTEN), uint32_t) & BM_DDR_CR57_ODTALTEN)

#ifndef __LANGUAGE_ASM__
//! @brief Set the ODTALTEN field to a new value.
#define BW_DDR_CR57_ODTALTEN(v) (BITBAND_ACCESS32(HW_DDR_CR57_ADDR, BP_DDR_CR57_ODTALTEN) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR58 - DDR Control Register 58
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR58 - DDR Control Register 58 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr58
{
    uint32_t U;
    struct _hw_ddr_cr58_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr58_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR58 register
 */
//@{
#define HW_DDR_CR58_ADDR         (REGS_DDR_BASE + 0xE8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR58              (*(__I hw_ddr_cr58_t *) HW_DDR_CR58_ADDR)
#define HW_DDR_CR58_RD()         (HW_DDR_CR58.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR58 bitfields
 */

/*!
 * @name Register DDR_CR58, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR58_Not_Used (0U)          //!< Bit position for DDR_CR58_Not_Used.
#define BM_DDR_CR58_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR58_Not_Used.
#define BS_DDR_CR58_Not_Used (16U)         //!< Bit field size in bits for DDR_CR58_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR58_Not_Used field.
#define BR_DDR_CR58_Not_Used (HW_DDR_CR58.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR58, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR58_NOT_USED (16U)         //!< Bit position for DDR_CR58_NOT_USED.
#define BM_DDR_CR58_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR58_NOT_USED.
#define BS_DDR_CR58_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR58_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR58_NOT_USED field.
#define BR_DDR_CR58_NOT_USED (HW_DDR_CR58.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR59 - DDR Control Register 59
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR59 - DDR Control Register 59 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr59
{
    uint32_t U;
    struct _hw_ddr_cr59_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr59_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR59 register
 */
//@{
#define HW_DDR_CR59_ADDR         (REGS_DDR_BASE + 0xECU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR59              (*(__I hw_ddr_cr59_t *) HW_DDR_CR59_ADDR)
#define HW_DDR_CR59_RD()         (HW_DDR_CR59.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR59 bitfields
 */

/*!
 * @name Register DDR_CR59, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR59_Not_Used (0U)          //!< Bit position for DDR_CR59_Not_Used.
#define BM_DDR_CR59_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR59_Not_Used.
#define BS_DDR_CR59_Not_Used (16U)         //!< Bit field size in bits for DDR_CR59_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR59_Not_Used field.
#define BR_DDR_CR59_Not_Used (HW_DDR_CR59.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR59, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR59_NOT_USED (16U)         //!< Bit position for DDR_CR59_NOT_USED.
#define BM_DDR_CR59_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR59_NOT_USED.
#define BS_DDR_CR59_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR59_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR59_NOT_USED field.
#define BR_DDR_CR59_NOT_USED (HW_DDR_CR59.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR60 - DDR Control Register 60
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR60 - DDR Control Register 60 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr60
{
    uint32_t U;
    struct _hw_ddr_cr60_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr60_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR60 register
 */
//@{
#define HW_DDR_CR60_ADDR         (REGS_DDR_BASE + 0xF0U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR60              (*(__I hw_ddr_cr60_t *) HW_DDR_CR60_ADDR)
#define HW_DDR_CR60_RD()         (HW_DDR_CR60.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR60 bitfields
 */

/*!
 * @name Register DDR_CR60, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR60_Not_Used (0U)          //!< Bit position for DDR_CR60_Not_Used.
#define BM_DDR_CR60_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR60_Not_Used.
#define BS_DDR_CR60_Not_Used (16U)         //!< Bit field size in bits for DDR_CR60_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR60_Not_Used field.
#define BR_DDR_CR60_Not_Used (HW_DDR_CR60.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR60, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR60_NOT_USED (16U)         //!< Bit position for DDR_CR60_NOT_USED.
#define BM_DDR_CR60_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR60_NOT_USED.
#define BS_DDR_CR60_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR60_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR60_NOT_USED field.
#define BR_DDR_CR60_NOT_USED (HW_DDR_CR60.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR61 - DDR Control Register 61
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR61 - DDR Control Register 61 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr61
{
    uint32_t U;
    struct _hw_ddr_cr61_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr61_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR61 register
 */
//@{
#define HW_DDR_CR61_ADDR         (REGS_DDR_BASE + 0xF4U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR61              (*(__I hw_ddr_cr61_t *) HW_DDR_CR61_ADDR)
#define HW_DDR_CR61_RD()         (HW_DDR_CR61.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR61 bitfields
 */

/*!
 * @name Register DDR_CR61, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR61_Not_Used (0U)          //!< Bit position for DDR_CR61_Not_Used.
#define BM_DDR_CR61_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR61_Not_Used.
#define BS_DDR_CR61_Not_Used (16U)         //!< Bit field size in bits for DDR_CR61_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR61_Not_Used field.
#define BR_DDR_CR61_Not_Used (HW_DDR_CR61.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR61, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR61_NOT_USED (16U)         //!< Bit position for DDR_CR61_NOT_USED.
#define BM_DDR_CR61_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR61_NOT_USED.
#define BS_DDR_CR61_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR61_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR61_NOT_USED field.
#define BR_DDR_CR61_NOT_USED (HW_DDR_CR61.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR62 - DDR Control Register 62
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR62 - DDR Control Register 62 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr62
{
    uint32_t U;
    struct _hw_ddr_cr62_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr62_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR62 register
 */
//@{
#define HW_DDR_CR62_ADDR         (REGS_DDR_BASE + 0xF8U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR62              (*(__I hw_ddr_cr62_t *) HW_DDR_CR62_ADDR)
#define HW_DDR_CR62_RD()         (HW_DDR_CR62.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR62 bitfields
 */

/*!
 * @name Register DDR_CR62, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR62_Not_Used (0U)          //!< Bit position for DDR_CR62_Not_Used.
#define BM_DDR_CR62_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR62_Not_Used.
#define BS_DDR_CR62_Not_Used (16U)         //!< Bit field size in bits for DDR_CR62_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR62_Not_Used field.
#define BR_DDR_CR62_Not_Used (HW_DDR_CR62.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR62, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR62_NOT_USED (16U)         //!< Bit position for DDR_CR62_NOT_USED.
#define BM_DDR_CR62_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR62_NOT_USED.
#define BS_DDR_CR62_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR62_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR62_NOT_USED field.
#define BR_DDR_CR62_NOT_USED (HW_DDR_CR62.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_CR63 - DDR Control Register 63
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_CR63 - DDR Control Register 63 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_ddr_cr63
{
    uint32_t U;
    struct _hw_ddr_cr63_bitfields
    {
        uint32_t Not_Used : 16;        //!< [15:0] Reserved
        uint32_t NOT_USED : 16;        //!< [31:16] Reserved
    } B;
} hw_ddr_cr63_t;
#endif

/*!
 * @name Constants and macros for entire DDR_CR63 register
 */
//@{
#define HW_DDR_CR63_ADDR         (REGS_DDR_BASE + 0xFCU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_CR63              (*(__I hw_ddr_cr63_t *) HW_DDR_CR63_ADDR)
#define HW_DDR_CR63_RD()         (HW_DDR_CR63.U)
#endif
//@}

/*
 * Constants & macros for individual DDR_CR63 bitfields
 */

/*!
 * @name Register DDR_CR63, field Not_Used[15:0] (ROZ)
 */
//@{
#define BP_DDR_CR63_Not_Used (0U)          //!< Bit position for DDR_CR63_Not_Used.
#define BM_DDR_CR63_Not_Used (0x0000FFFFU) //!< Bit mask for DDR_CR63_Not_Used.
#define BS_DDR_CR63_Not_Used (16U)         //!< Bit field size in bits for DDR_CR63_Not_Used.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR63_Not_Used field.
#define BR_DDR_CR63_Not_Used (HW_DDR_CR63.B.Not_Used)
#endif
//@}

/*!
 * @name Register DDR_CR63, field NOT_USED[31:16] (ROZ)
 */
//@{
#define BP_DDR_CR63_NOT_USED (16U)         //!< Bit position for DDR_CR63_NOT_USED.
#define BM_DDR_CR63_NOT_USED (0xFFFF0000U) //!< Bit mask for DDR_CR63_NOT_USED.
#define BS_DDR_CR63_NOT_USED (16U)         //!< Bit field size in bits for DDR_CR63_NOT_USED.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_CR63_NOT_USED field.
#define BR_DDR_CR63_NOT_USED (HW_DDR_CR63.B.NOT_USED)
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_RCR - RCR Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_RCR - RCR Control Register (RW)
 *
 * Reset value: 0x00000000U
 *
 * This is a PHY register. It controls the operation of the read clock recovery
 * module.
 */
typedef union _hw_ddr_rcr
{
    uint32_t U;
    struct _hw_ddr_rcr_bitfields
    {
        uint32_t RESERVED0 : 30;       //!< [29:0]
        uint32_t RST : 1;              //!< [30] Reset
        uint32_t RESERVED1 : 1;        //!< [31]
    } B;
} hw_ddr_rcr_t;
#endif

/*!
 * @name Constants and macros for entire DDR_RCR register
 */
//@{
#define HW_DDR_RCR_ADDR          (REGS_DDR_BASE + 0x180U)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_RCR               (*(__IO hw_ddr_rcr_t *) HW_DDR_RCR_ADDR)
#define HW_DDR_RCR_RD()          (HW_DDR_RCR.U)
#define HW_DDR_RCR_WR(v)         (HW_DDR_RCR.U = (v))
#define HW_DDR_RCR_SET(v)        (HW_DDR_RCR_WR(HW_DDR_RCR_RD() |  (v)))
#define HW_DDR_RCR_CLR(v)        (HW_DDR_RCR_WR(HW_DDR_RCR_RD() & ~(v)))
#define HW_DDR_RCR_TOG(v)        (HW_DDR_RCR_WR(HW_DDR_RCR_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_RCR bitfields
 */

/*!
 * @name Register DDR_RCR, field RST[30] (WO)
 *
 * Read clock recovery module reset. Used to force RCR software reset in
 * addition to system reset.
 *
 * Values:
 * - 0 - No software reset
 * - 1 - Force software reset
 */
//@{
#define BP_DDR_RCR_RST       (30U)         //!< Bit position for DDR_RCR_RST.
#define BM_DDR_RCR_RST       (0x40000000U) //!< Bit mask for DDR_RCR_RST.
#define BS_DDR_RCR_RST       (1U)          //!< Bit field size in bits for DDR_RCR_RST.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_RCR_RST field.
#define BR_DDR_RCR_RST       (BITBAND_ACCESS32(HW_DDR_RCR_ADDR, BP_DDR_RCR_RST))
#endif

//! @brief Format value for bitfield DDR_RCR_RST.
#define BF_DDR_RCR_RST(v)    (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_RCR_RST), uint32_t) & BM_DDR_RCR_RST)

#ifndef __LANGUAGE_ASM__
//! @brief Set the RST field to a new value.
#define BW_DDR_RCR_RST(v)    (BITBAND_ACCESS32(HW_DDR_RCR_ADDR, BP_DDR_RCR_RST) = (v))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_DDR_PAD_CTRL - I/O Pad Control Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_DDR_PAD_CTRL - I/O Pad Control Register (RW)
 *
 * Reset value: 0x00000200U
 */
typedef union _hw_ddr_pad_ctrl
{
    uint32_t U;
    struct _hw_ddr_pad_ctrl_bitfields
    {
        uint32_t SPARE_DLY_CTRL : 4;   //!< [3:0] These SPARE_DLY_CTRL[3:0]bits
                                       //! set the delay chains in the spare logic.
        uint32_t RESERVED0 : 20;       //!< [23:4] Reserved
        uint32_t PAD_ODT_CS0 : 2;      //!< [25:24] Required to enable ODT and
                                       //! configure ODT resistor value in the pad.
        uint32_t RESERVED1 : 6;        //!< [31:26] Reserved
    } B;
} hw_ddr_pad_ctrl_t;
#endif

/*!
 * @name Constants and macros for entire DDR_PAD_CTRL register
 */
//@{
#define HW_DDR_PAD_CTRL_ADDR     (REGS_DDR_BASE + 0x1ACU)

#ifndef __LANGUAGE_ASM__
#define HW_DDR_PAD_CTRL          (*(__IO hw_ddr_pad_ctrl_t *) HW_DDR_PAD_CTRL_ADDR)
#define HW_DDR_PAD_CTRL_RD()     (HW_DDR_PAD_CTRL.U)
#define HW_DDR_PAD_CTRL_WR(v)    (HW_DDR_PAD_CTRL.U = (v))
#define HW_DDR_PAD_CTRL_SET(v)   (HW_DDR_PAD_CTRL_WR(HW_DDR_PAD_CTRL_RD() |  (v)))
#define HW_DDR_PAD_CTRL_CLR(v)   (HW_DDR_PAD_CTRL_WR(HW_DDR_PAD_CTRL_RD() & ~(v)))
#define HW_DDR_PAD_CTRL_TOG(v)   (HW_DDR_PAD_CTRL_WR(HW_DDR_PAD_CTRL_RD() ^  (v)))
#endif
//@}

/*
 * Constants & macros for individual DDR_PAD_CTRL bitfields
 */

/*!
 * @name Register DDR_PAD_CTRL, field SPARE_DLY_CTRL[3:0] (RW)
 *
 * SPARE_DLY_CTRL[1:0] is used to control the delay chain #0. 00 No buffer, only
 * mux delay 01 4 buffers 10 7 buffers 11 10 buffers SPARE_DLY_CTRL[3:2] is not
 * used. Do not write to this bit field. Read access can fail if
 * SPARE_DLY_CTRL[1:0] = 00. Use SPARE_DLY_CTRL[1:0] = 01 instead.
 */
//@{
#define BP_DDR_PAD_CTRL_SPARE_DLY_CTRL (0U) //!< Bit position for DDR_PAD_CTRL_SPARE_DLY_CTRL.
#define BM_DDR_PAD_CTRL_SPARE_DLY_CTRL (0x0000000FU) //!< Bit mask for DDR_PAD_CTRL_SPARE_DLY_CTRL.
#define BS_DDR_PAD_CTRL_SPARE_DLY_CTRL (4U) //!< Bit field size in bits for DDR_PAD_CTRL_SPARE_DLY_CTRL.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_PAD_CTRL_SPARE_DLY_CTRL field.
#define BR_DDR_PAD_CTRL_SPARE_DLY_CTRL (HW_DDR_PAD_CTRL.B.SPARE_DLY_CTRL)
#endif

//! @brief Format value for bitfield DDR_PAD_CTRL_SPARE_DLY_CTRL.
#define BF_DDR_PAD_CTRL_SPARE_DLY_CTRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_PAD_CTRL_SPARE_DLY_CTRL), uint32_t) & BM_DDR_PAD_CTRL_SPARE_DLY_CTRL)

#ifndef __LANGUAGE_ASM__
//! @brief Set the SPARE_DLY_CTRL field to a new value.
#define BW_DDR_PAD_CTRL_SPARE_DLY_CTRL(v) (HW_DDR_PAD_CTRL_WR((HW_DDR_PAD_CTRL_RD() & ~BM_DDR_PAD_CTRL_SPARE_DLY_CTRL) | BF_DDR_PAD_CTRL_SPARE_DLY_CTRL(v)))
#endif
//@}

/*!
 * @name Register DDR_PAD_CTRL, field PAD_ODT_CS0[25:24] (RW)
 *
 * On Die Termination of the pads when the Read command is issued to chip select
 * 0. This version of the PHY cannot supports different pad ODT settings when
 * external chip-selects have different drive capability. The PHY will use only the
 * PAD_ODT_CS0 setting for the pad's ODT resistor. The user needs to disable the
 * pads for low power mode operation.
 *
 * Values:
 * - 00 - ODT Disabled
 * - 01 - 75 Ohms
 * - 10 - 150 Ohms
 * - 11 - 50 Ohms
 */
//@{
#define BP_DDR_PAD_CTRL_PAD_ODT_CS0 (24U)  //!< Bit position for DDR_PAD_CTRL_PAD_ODT_CS0.
#define BM_DDR_PAD_CTRL_PAD_ODT_CS0 (0x03000000U) //!< Bit mask for DDR_PAD_CTRL_PAD_ODT_CS0.
#define BS_DDR_PAD_CTRL_PAD_ODT_CS0 (2U)   //!< Bit field size in bits for DDR_PAD_CTRL_PAD_ODT_CS0.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the DDR_PAD_CTRL_PAD_ODT_CS0 field.
#define BR_DDR_PAD_CTRL_PAD_ODT_CS0 (HW_DDR_PAD_CTRL.B.PAD_ODT_CS0)
#endif

//! @brief Format value for bitfield DDR_PAD_CTRL_PAD_ODT_CS0.
#define BF_DDR_PAD_CTRL_PAD_ODT_CS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DDR_PAD_CTRL_PAD_ODT_CS0), uint32_t) & BM_DDR_PAD_CTRL_PAD_ODT_CS0)

#ifndef __LANGUAGE_ASM__
//! @brief Set the PAD_ODT_CS0 field to a new value.
#define BW_DDR_PAD_CTRL_PAD_ODT_CS0(v) (HW_DDR_PAD_CTRL_WR((HW_DDR_PAD_CTRL_RD() & ~BM_DDR_PAD_CTRL_PAD_ODT_CS0) | BF_DDR_PAD_CTRL_PAD_ODT_CS0(v)))
#endif
//@}

//-------------------------------------------------------------------------------------------
// hw_ddr_t - module struct
//-------------------------------------------------------------------------------------------
/*!
 * @brief All DDR module registers.
 */
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_ddr
{
    __IO hw_ddr_cr00_t CR00;               //!< [0x0] DDR Control Register 0
    __I hw_ddr_cr01_t CR01;                //!< [0x4] DDR Control Register 1
    __IO hw_ddr_cr02_t CR02;               //!< [0x8] DDR Control Register 2
    __IO hw_ddr_cr03_t CR03;               //!< [0xC] DDR Control Register 3
    __IO hw_ddr_cr04_t CR04;               //!< [0x10] DDR Control Register 4
    __IO hw_ddr_cr05_t CR05;               //!< [0x14] DDR Control Register 5
    __IO hw_ddr_cr06_t CR06;               //!< [0x18] DDR Control Register 6
    __IO hw_ddr_cr07_t CR07;               //!< [0x1C] DDR Control Register 7
    __IO hw_ddr_cr08_t CR08;               //!< [0x20] DDR Control Register 8
    __IO hw_ddr_cr09_t CR09;               //!< [0x24] DDR Control Register 9
    __IO hw_ddr_cr10_t CR10;               //!< [0x28] DDR Control Register 10
    __IO hw_ddr_cr11_t CR11;               //!< [0x2C] DDR Control Register 11
    __IO hw_ddr_cr12_t CR12;               //!< [0x30] DDR Control Register 12
    __IO hw_ddr_cr13_t CR13;               //!< [0x34] DDR Control Register 13
    __IO hw_ddr_cr14_t CR14;               //!< [0x38] DDR Control Register 14
    __IO hw_ddr_cr15_t CR15;               //!< [0x3C] DDR Control Register 15
    __IO hw_ddr_cr16_t CR16;               //!< [0x40] DDR Control Register 16
    __IO hw_ddr_cr17_t CR17;               //!< [0x44] DDR Control Register 17
    __IO hw_ddr_cr18_t CR18;               //!< [0x48] DDR Control Register 18
    __IO hw_ddr_cr19_t CR19;               //!< [0x4C] DDR Control Register 19
    __IO hw_ddr_cr20_t CR20;               //!< [0x50] DDR Control Register 20
    __IO hw_ddr_cr21_t CR21;               //!< [0x54] DDR Control Register 21
    __IO hw_ddr_cr22_t CR22;               //!< [0x58] DDR Control Register 22
    __I hw_ddr_cr23_t CR23;                //!< [0x5C] DDR Control Register 23
    __I hw_ddr_cr24_t CR24;                //!< [0x60] DDR Control Register 24
    __IO hw_ddr_cr25_t CR25;               //!< [0x64] DDR Control Register 25
    __IO hw_ddr_cr26_t CR26;               //!< [0x68] DDR Control Register 26
    __IO hw_ddr_cr27_t CR27;               //!< [0x6C] DDR Control Register 27
    __IO hw_ddr_cr28_t CR28;               //!< [0x70] DDR Control Register 28
    __IO hw_ddr_cr29_t CR29;               //!< [0x74] DDR Control Register 29
    __IO hw_ddr_cr30_t CR30;               //!< [0x78] DDR Control Register 30
    __IO hw_ddr_cr31_t CR31;               //!< [0x7C] DDR Control Register 31
    __I hw_ddr_cr32_t CR32;                //!< [0x80] DDR Control Register 32
    __I hw_ddr_cr33_t CR33;                //!< [0x84] DDR Control Register 33
    __IO hw_ddr_cr34_t CR34;               //!< [0x88] DDR Control Register 34
    __I hw_ddr_cr35_t CR35;                //!< [0x8C] DDR Control Register 35
    __I hw_ddr_cr36_t CR36;                //!< [0x90] DDR Control Register 36
    __IO hw_ddr_cr37_t CR37;               //!< [0x94] DDR Control Register 37
    __IO hw_ddr_cr38_t CR38;               //!< [0x98] DDR Control Register 38
    __IO hw_ddr_cr39_t CR39;               //!< [0x9C] DDR Control Register 39
    __IO hw_ddr_cr40_t CR40;               //!< [0xA0] DDR Control Register 40
    __IO hw_ddr_cr41_t CR41;               //!< [0xA4] DDR Control Register 41
    __IO hw_ddr_cr42_t CR42;               //!< [0xA8] DDR Control Register 42
    __IO hw_ddr_cr43_t CR43;               //!< [0xAC] DDR Control Register 43
    __IO hw_ddr_cr44_t CR44;               //!< [0xB0] DDR Control Register 44
    __IO hw_ddr_cr45_t CR45;               //!< [0xB4] DDR Control Register 45
    __IO hw_ddr_cr46_t CR46;               //!< [0xB8] DDR Control Register 46
    __IO hw_ddr_cr47_t CR47;               //!< [0xBC] DDR Control Register 47
    __IO hw_ddr_cr48_t CR48;               //!< [0xC0] DDR Control Register 48
    __IO hw_ddr_cr49_t CR49;               //!< [0xC4] DDR Control Register 49
    __IO hw_ddr_cr50_t CR50;               //!< [0xC8] DDR Control Register 50
    __IO hw_ddr_cr51_t CR51;               //!< [0xCC] DDR Control Register 51
    __IO hw_ddr_cr52_t CR52;               //!< [0xD0] DDR Control Register 52
    __IO hw_ddr_cr53_t CR53;               //!< [0xD4] DDR Control Register 53
    __IO hw_ddr_cr54_t CR54;               //!< [0xD8] DDR Control Register 54
    __IO hw_ddr_cr55_t CR55;               //!< [0xDC] DDR Control Register 55
    __IO hw_ddr_cr56_t CR56;               //!< [0xE0] DDR Control Register 56
    __IO hw_ddr_cr57_t CR57;               //!< [0xE4] DDR Control Register 57
    __I hw_ddr_cr58_t CR58;                //!< [0xE8] DDR Control Register 58
    __I hw_ddr_cr59_t CR59;                //!< [0xEC] DDR Control Register 59
    __I hw_ddr_cr60_t CR60;                //!< [0xF0] DDR Control Register 60
    __I hw_ddr_cr61_t CR61;                //!< [0xF4] DDR Control Register 61
    __I hw_ddr_cr62_t CR62;                //!< [0xF8] DDR Control Register 62
    __I hw_ddr_cr63_t CR63;                //!< [0xFC] DDR Control Register 63
    uint8_t _reserved0[128];
    __IO hw_ddr_rcr_t RCR;                 //!< [0x180] RCR Control Register
    uint8_t _reserved1[40];
    __IO hw_ddr_pad_ctrl_t PAD_CTRL;       //!< [0x1AC] I/O Pad Control Register
} hw_ddr_t;
#pragma pack()

//! @brief Macro to access all DDR registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//!     use the '&' operator, like <code>&HW_DDR</code>.
#define HW_DDR         (*(hw_ddr_t *) REGS_DDR_BASE)
#endif

#endif // __HW_DDR_REGISTERS_H__
// v22/130726/0.9
// EOF
